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semicmf.019 1 features ? eight gigabit ports with gmii and pcs interface ? gigabit port can also support 100/10 mbps mii interface ? two gigabit ports can be aggregated into a 2gbps stacking port working with vtx2600 in stacking mode. ? high performance layer 2 packet forwarding (11.904m packets per second) and filtering at full-wire speed ? maximum throughput is 8 gbps non-blocking ? centralized shared-memory architecture ? consists of two memory domains at 133 mhz ? frame buffer domain: two banks of zbt-sram with 2m/4mb total ? switch database domain with 256k/512k sram ? up to 64k mac addresses to provide large node aggregation in wiring closet switches traffic classification ? classify traffic into 8 transmission priorities per port ? supports delay bounded, strict priority and wfq ? provides 2 level dropping precedence with wred mechanism ? user controlled thresholds for wred ? classification based on layer 2, 3 markings ? vlan priority field in vlan tagged frame ? ds/tos field in ip packet ? the precedence of above two classifications can be programmable qos support ? supports ieee 802.1p/q quality of service with 8 priority ? buffer management: reserve buffers on per class and per port basis ds5750 issue 1 july 2002 ordering information MVTX2803Ag 596 pin bga -40c to 85c figure 1 - MVTX2803Ag block diagram frame data buffer a zbt-sram (1m/2mb) frame data buffer b zbt-sram (1m/2mb) sram 256/512k sw database schedule gmii /pcs port 0 gmii /pcs port 1 gmii /pcs port 2 gmii /pcs port 3 gmii /pcs port 4 gmii /pcs port 5 gmii /pcs port 6 gmii /pcs port 7 nm database fdb interface sdb interface mvtx2803 mac table led frame engine search engine 32-bit 64-bit 64-bit management module serial / i 2 c MVTX2803Ag 8-port 1000 mbps et hernet distributed switch data sheet
MVTX2803Ag data sheet semicmf.019 2 ? port-based priority: vlan priority with tagged fram e can be overwritten by the priority of pvid ? qos features can be configured on a per port basis ? full duplex ethernet ie ee 802.3x flow control ? provides ethernet multicast and broadcast control ? 4 port trunking groups, max of 3 ports per group (trunking can be based on source mac and/or destination mac and source port) ? led signals provided by a seri al or parallel interface ? synchronous serial interface and i2c interface in unmanaged mode. ? hardware auto-negotiation through serial management interface (mdio) for gigabit ethernet ports, supports 10/100/1000 mbps ? bist for internal and external sram-zbt ?i 2 c eeprom or synchronous serial port for configuration ? packaged in 596-pin bga description the mvtx2800ag family is a group of 8-port 1000 mb ps non-blocking ethernet switch chips with on-chip address memory. a single chip provides a maximum of eight 1000 mbps ports and a dedicated cpu interface with a 16/8 bit bus for managed and unmanaged switch applicat ions. the vtx2800 family consists of the following four products: ? vtx2804 8 gigabit ports managed ? vtx2803 8 gigabit ports unmanaged ? vtx2802 4 gigabit ports managed ? vtx2801 4 gigabit ports unmanaged the MVTX2803Ag supports up to 64k mac addresses to ag gregate traffic from multiple wiring closet stacks. the centralized shared-memory architecture allows a very high performance packet-forwarding rate of 11.904m packets per second at full wire speed. the chip is optimized to provide a low-cost, high performance workgroup, and wiring closet, layer 2 switch ing solution with 8 gigabit ethernet ports. two frame buffer memory domains utilize cost effective, high?performance zbt-sram with aggregated bandwidth of 16gbps to support full wire speed on all external ports simultaneously. with strict priority, delay bounded, and wrr trans mission scheduling, plus wred memory congestion scheme, the chip provides powerful qos functions fo r convergent network multimedia and mission-critical applications. the chip provides 8 tr ansmission priorities and 2 level dr op precedence. traffic is assigned its transmission priority and dropping precedence based on the frame vlan tag priority. the MVTX2803Ag supports port trunking/load sharing on t he 1000 mbps ports with fail-over capability. the port trunking/load sharing can be used to group ports betw een interlinked switches to increase the effective network bandwidth. in full-duplex mode, ieee 802.3x flow control is prov ided. the physical coding sublayer (pcs) is integrated on-chip to provide a direct 10-bit gmii interface, or the pcs can be bypassed to provide an interface to existing fiber-based gigabit ethernet transceivers. the MVTX2803Ag is fabricated using 0.25 m technology. inputs, however, are 3.3v tolerant and the outputs are capable of directly interfacing to lvttl levels. the MVTX2803Ag is packaged in a 596-pin ball grid array package.
data sheet MVTX2803Ag semicmf.xxx i table of contents 1.0 block functionality ..... ................. ................ ................ ................. ................ ................. ..... 5 1.1 frame data buffer (fdb) interfaces ......................................................................................... ....................5 1.2 switch database (sdb) inte rface............................................................................................ ......................5 1.3 gmii/pcs mac module (gmac) ................................................................................................ .................5 1.4 frame engine .............................................................................................................. .................................5 1.5 search engine ............................................................................................................. .................................5 1.6 led interface .............................................................................................................. ..................................5 1.7 internal memory ........................................................................................................... ................................5 2.0 system configuration............... ................. ................ .............. .............. .............. ............. .. 5 2.1 i 2 c interface .................................................................................................................... ..............................5 2.1.1 start condition .......................................................................................................... ...........................6 2.1.2 address.................................................................................................................. ..............................6 2.1.3 data direction ........................................................................................................... ...........................6 2.1.4 acknowledgment ........................................................................................................... ......................6 2.1.5 data ..................................................................................................................... ................................6 2.1.6 stop condition ........................................................................................................... ..........................6 2.2 synchronous serial interface ............................................................................................... .........................6 2.2.1 write command ............................................................................................................ .......................7 2.2.2 read command............................................................................................................. ......................7 3.0 data forwarding protocol ............... .............. .............. ............... .............. .............. ............ 7 3.1 unicast data frame forwarding .............................................................................................. .....................7 3.2 multicast data frame forwarding ........................................................................................... .....................8 4.0 memory interface ........ ................. ................ ................ ................. ................ ................. ..... 8 4.1 overview .................................................................................................................. ....................................8 4.2 detailed memory information . ............................................................................................... ........................9 5.0 search engine ............. ................. ................ ................ ................. ................ ............... ....... 9 5.1 search engine overview ........................... ......................................................................... ..........................9 5.2 basic flow ................................................................................................................. ....................................9 5.3 search, learning, and aging ................................................................................................ .......................10 5.3.1 mac search ............................................................................................................... .......................10 5.3.2 learning ................................................................................................................. ............................10 5.3.3 aging.................................................................................................................... ..............................10 5.3.4 data structure........................................................................................................... .........................10 6.0 frame engine .............. ................. ................ ................ ................. ................ ............... ..... 10 6.1 data forwarding summary ................................................................................................... .....................10 6.2 frame engine details....................................................................................................... ...........................11 6.2.1 fcb manager .............................................................................................................. ......................11 6.2.2 rx interface ............................................................................................................. ..........................11 6.2.3 rxdma .................................................................................................................... ..........................11 6.2.4 txq manager .............................................................................................................. .......................11 6.3 port control ............................................................................................................... ..................................11 6.4 txdma ...................................................................................................................... ..................................11 7.0 quality of service and flow cont rol ............... .............. .............. .............. .............. ........ 11 7.1 model ..................................................................................................................... .....................................11 7.2 four qos configurations.................................................................................................... .........................13 7.3 delay bound................................................................................................................ ................................13 7.4 strict priority and best effort ............................................................................................ ...........................13 7.5 weighted fair queuing ...................................................................................................... .........................14
MVTX2803Ag data sheet ii semicmf.xxx 7.6 shaper ..................................................................................................................... ............................. 14 7.7 wred drop threshold management support .................................................................................... 14 7.8 buffer management .......................................................................................................... .................... 15 7.8.1 dropping when buffers are scarce ......................................................................................... ... 16 7.9 MVTX2803Ag flow control basics............................................................................................. ......... 16 7.9.1 unicast flow control..................................................................................................... .............. 17 7.9.2 multicast flow control................................................................................................... .............. 17 7.10 mapping to ietf diffserv classes .......................................................................................... ............ 17 8.0 port trunking............. ................. ................ ................ ................. ................ ............... .18 8.1 features and restrictions ................................................................................................. ................... 18 8.2 unicast packet forwarding ................................................................................................. ................. 18 8.3 multicast packet forwarding ................................................................................................ ................ 19 8.4 preventing multicast packets fr om looping back to the source tr unk................................................ 19 9.0 led interface ..... ................. ................ ................ .............. ............... .............. ............ .19 9.1 introduction .............................................................................................................. ............................ 19 9.2 serial mode ................................................................................................................ .......................... 19 9.3 parallel mode.............................................................................................................. .......................... 20 9.4 led control registers...................................................................................................... .................... 20 10.0 register definition ..... ................ ................ ................. ................ ................. ............. 21 10.1 MVTX2803Ag register description .................. ......................................................................... ........ 21 10.2 group 0 address - mac ports group................ ......................................................................... ........ 29 10.2.1 ecr1pn: port n control register ................ ......................................................................... .... 29 10.2.2 ecr2pn: port n control register ................ ......................................................................... .... 31 10.2.3 ecrmisc1 ? cpu port control register mi sc1 ..................................................................... 32 10.2.4 ecrmisc2 ? cpu port control register mi sc2 ..................................................................... 32 10.2.5 ggcontrol 0? extra giga port control ....... ............................................................................. 32 10.2.6 ggcontrol 1? extra giga port control ....... ............................................................................. 33 10.2.7 ggcontrol 2? extra giga port control ....... ............................................................................. 33 10.2.8 ggcontrol 3? extra giga port control ....... ............................................................................. 34 10.3 group 1 address - vlan group..................... ......................................................................... ........... 35 10.3.1avtcl ? vlan type code register low ................................................................................. 35 10.3.2 avtch ? vlan type code register high ............................................................................... 35 10.3.3 pvmap00_0 ? port 00 configuration register 0 ...................................................................... 35 10.3.4 pvmap00_1 ? port 00 configuration register 1 ...................................................................... 35 10.3.5 pvmap00_2 ? port 00 configuration register 2 ...................................................................... 36 10.3.6 pvmap00_3 ? port 00 configuration register 3 ...................................................................... 36 10.3.7 pvmode .................................................................................................................. ................ 37 10.4 group 2 address - port trunking group......... ............................................................................ ........ 37 10.4.1 trunk0 ? trunk group 0 member (managed mo de only) ...................................................... 37 10.4.2 trunk1 ? trunk group 1 member (managed mo de only) ...................................................... 38 10.4.3 trunk2? trunk group 2 mem ber (managed mode only) ....................................................... 38 10.4.4 trunk3? trunk group 3 mem ber (managed mode only) ....................................................... 38 10.4.5 trunk_hash_mode ? trunk hash mode ............................................................................. 38 10.4.6 trunk0_mode ? trunk group 0 and 1 mode ........................................................................ 38 10.4.7 trunk0_hash0 ? trunk group 0 hash result 0,1,2 destination port number ......................... 38 10.4.8 trunk0_hash1 ? trunk group 0 hash result 2,3,4,5 destination port number ...................... 39 10.4.9 trunk0_hash2 ? trunk group 0 hash result 5,6,7 destination port number ......................... 39 10.4.10 trunk0_hash3 ? trunk grou p 0 hash result 8,9,10 destinat ion port number ..................... 39 10.4.11 trunk0_hash4 ? trunk grou p 0 hash result 10,11,12,13 de stination port number ............ 39 10.4.12 trunk0_hash5 ? trunk grou p 0 hash result 13,14,15 destinat ion port number ................. 39 10.4.13 trunk1_mode ? trunk group 1 mode (unm anaged mode) ............................................... 39 10.4.14 trunk1_hash0 ? trun k group 1 hash result 0, 1, 2 dest ination port number ..................... 39
data sheet MVTX2803Ag semicmf.xxx iii 10.4.15 trunk1_hash1 ? trunk group 1 hash result 2, 3, 4, 5 destination port number........................40 10.4.16 trunk1_hash2 ? trunk grou p 1 hash result 5, 6, 7 destination port number............................40 10.4.17 trunk1_hash3 ? trunk group 1 hash result 8, 9, 10 destination port number..........................40 10.4.18 trunk1_hash4? trunk group 1 hash result 11, 12, 13 destinat ion port number ......................40 10.4.19 trunk1_hash5 ? trunk group 1 hash result 13, 14, 15 destinati on port number .....................40 10.4.20 trunk2_hash0 ? trunk grou p 2 hash result 0, 1, 2 destination port number............................40 10.4.21 trunk2_hash1 ? trunk group 2 hash result 2, 3, 4, 5 destination port number........................40 10.4.22 trunk2_hash2 ? trunk grou p 2 hash result 5, 6, 7 destination port number............................40 10.4.23 trunk2_hash3 ? trunk group 2 hash result 8, 9, 10 destination port number..........................40 10.4.24 trunk2_hash4 ? trunk grou p 2 hash result 10, 11, 12, 13 destination port number................40 10.4.25 trunk2_hash5 ? trunk group 2 hash result 13, 14, 15 destina tion port number......................40 10.4.26 trunk3_hash0 ? trunk grou p 3 hash result 0, 1, 2 destination port number............................41 10.4.27 trunk3_hash1 ? trunk group 3 hash result 2, 3, 4, 5 destination port number........................41 10.4.28 trunk3_hash2 ? trunk grou p 3 hash result 5, 6, 7 destination port number............................41 10.4.29 trunk3_hash3 ? trunk group 3 hash result 8, 9, 10 destination port number..........................41 10.4.30 trunk3_hash4 ? trunk grou p 3 hash result 10, 11, 12, 13 destination port number................41 10.4.31 trunk3_hash5 ? trunk group 3 hash result 13, 14, 15 destina tion port number......................41 10.4.32 multicast hash registers ..................... .......................................................................... ................41 10.4.33 multicast_hash00 ? multicast hash result0 mask byte [7:0].........................................................41 10.4.34 multicast_hash01 ? multicast hash result1 mask byte [7:0].........................................................41 10.4.35 multicast_hash02 ? multicast hash result2 mask byte [7:0].........................................................41 10.4.36 multicast_hash03 ? multicast hash result3 mask byte [7:0].........................................................42 10.4.37 multicast_hash04 ? multicast hash result4 ma sk byte [7:0]........................................................42 10.4.38 multicast_hash05 ? multicast hash result5 mask byte [7:0].........................................................42 10.4.39 multicast_hash06 ? multicast hash result6 mask byte [7:0].........................................................42 10.4.40 multicast_hash07 ? multicast hash result7 mask byte [7:0].........................................................42 10.4.41 multicast_hash08 ? multicast hash result8 mask byte [7:0].........................................................42 10.4.42 multicast_hash09 ? multicast hash result9 mask byte [7:0].........................................................42 10.4.43 multicast_hash10 ? multicast hash result10 ma sk byte [7:0].......................................................42 10.4.44 multicast_hash11 ? multicast hash result11 ma sk byte [7:0].......................................................43 10.4.45 multicast_hash12 ? multicast hash result12 ma sk byte [7:0].......................................................43 10.4.46 multicast_hash13 ? multicast hash result13 ma sk byte [7:0].......................................................43 10.4.47 multicast_hash14 ? multicast hash result14 ma sk byte [7:0].......................................................43 10.4.48 multicast_hash15 ? multicast hash result15 ma sk byte [7:0].......................................................43 10.4.49 multicast_hashml ? multicas t hash bit[8] for result 7-0................................................................4 3 10.4.50 multicast_hashmh ? multicast hash bit[8] for result 15-8 ..........................................................43 10.5 group 3 address - cpu port configuration grou p ............................................................................ .......43 10.5.1 mac0 ? cpu mac address byte 0 ........................................................................................... ........43 10.5.2 mac1 ? cpu mac address byte 1 ........................................................................................... ........44 10.5.3 mac2 ? cpu mac address byte 2 ........................................................................................... ........44 10.5.4 mac3 ? cpu mac address byte 3 ........................................................................................... ........44 10.5.5 mac4 ? cpu mac address byte 4 ........................................................................................... ........44 10.5.6 mac5 ? cpu mac address byte 5 ........................................................................................... ........44 10.5.7 int_mask0 ? interrupt mask 0 ............................................................................................ ...........44 10.5.8 int_mask1 ? interrupt mask 1 ............................................................................................ ...........44 10.5.9 int_status0 ? masked interrupt status regist er0 ......................................................................44 10.5.10 int_status1 ? masked interr upt status register1 ....................................................................44 10.5.11 intp_mask0 ? interr upt mask for mac port 0, 1............. ................ ................ ................ .............4 4 10.5.12 intp_mask1 ? interr upt mask for mac port 2, 3............. ................ ................ ................ .............4 4 10.5.13 intp_mask4 ? interr upt mask for mac port 4, 5............. ................ ................ ................ .............4 5 10.5.14 intp_mask5 ? interr upt mask for mac port 6, 7............. ................ ................ ................ .............4 5 10.5.15 rqs ? receive queue select ............................................................................................. ..........45 10.5.16 rqss ? receive queue status............................................................................................ .........45 10.5.17 tx_age ? tx queue aging timer.......................................................................................... ........45
MVTX2803Ag data sheet iv semicmf.xxx 10.6 group 4 address - search engine group....... .............................................................................. ...... 45 10.6.1 agetime_low ? mac address aging time low..................................................................... 45 10.6.2 agetime_high ?mac address aging time high .................................................................... 45 10.6.3 v_agetime ? vlan to port aging time ................................................................................... 46 10.6.4 se_opmode ? search engine operation mode .................................................................... 46 10.6.5 scan ? scan control register ............................................................................................ ... 46 10.7 group 5 address - buffer cont rol/qos group ................................................................................ ... 46 10.7.1 fcbat ? fcb aging timer................................................................................................. ...... 46 10.7.2 qosc ? qos control...................................................................................................... ......... 47 10.7.3 fcr ? flooding control register ......................................................................................... .....47 10.7.4 avpml ? vlan priority map ................ ................ ................. ................ ................ .............. ..... 48 10.7.5 avpmm ? vlan priority map ............................................................................................... .... 48 10.7.6 avpmh ? vlan priority map ................ ................ ................. ................ ................ .............. ..... 49 10.7.7 ospml ? tos priority map ................................................................................................ ...... 49 10.7.8 tospmm ? tos priority map............................................................................................... .... 49 10.7.9 tospmh ? tos priority map ............................................................................................... .... 50 10.7.10 avdm ? vlan discard ma p ................................................................................................ ... 50 10.7.11 tosdml ? tos discard map ............................................................................................... .50 10.7.12 bmrc - broadcast/multicast rate control.............................................................................. 51 10.7.13 ucc ? unicast congestion control ....................................................................................... .52 10.7.14 mcc ? multicast congestion control ..................................................................................... .52 10.7.15 prg ? port reservation for giga ports.................................................................................. .52 10.7.16 sfcb ? share fcb size.................................................................................................. ....... 53 10.7.17 c2rs ? class 2 reserved size ........................................................................................... ...53 10.7.18 c3rs ? class 3 reserved size ........................................................................................... ...53 10.7.19 c4rs ? class 4 reserved size ........................................................................................... ...54 10.7.20 c5rs ? class 5 reserved size ........................................................................................... ...54 10.7.21 c6rs ? class 6 reserved size ........................................................................................... ...54 10.7.22 c7rs ? class 7 reserved size ........................................................................................... ...54 10.7.23 qosc00 ? byte_c2_g0.................................................................................................... ... 55 10.7.24 qosc01 ? byte_c3_g0.................................................................................................... ... 55 10.7.25 qosc02 ? byte_c4_g0.................................................................................................... ... 55 10.7.26 qosc03 ? byte_c5_g0.................................................................................................... ... 55 10.7.27 qosc04 ? byte_c6_g0.................................................................................................... ... 55 10.7.28 qosc05 ? byte_c7_g0.................................................................................................... ... 56 10.7.29 qosc06 ? byte_c2_g1.................................................................................................... ... 56 10.7.30 qosc07 ? byte_c3_g1.................................................................................................... ... 56 10.7.31 qosc08 ? byte_c4_g1.................................................................................................... ... 56 10.7.32 qosc09 ? byte_c5_g1.................................................................................................... ... 56 10.7.33 qosc0a ? byte_c6_g1 ............................... ..................................................................... .. 57 10.7.34 qosc0b ? byte_c7_g1 ............................... ..................................................................... .. 57 10.7.35 qosc0c ? byte_c2_g2 ............................... ..................................................................... .. 57 10.7.36 qosc0d ? byte_c3_g2 ............................... ..................................................................... .. 57 10.7.37 qosc0e ? byte_c4_g2 ............................... ..................................................................... .. 57 10.7.38 osc0f ? byte_c5_g2 ............................... ...................................................................... .... 58 10.7.39 qosc10 ? byte_c6_g2.................................................................................................... ... 58 10.7.40 qosc11 ? byte_c7_g2.................................................................................................... ... 58 10.7.41 qosc12 ? byte_c2_g3.................................................................................................... ... 58 10.7.42 qosc13 ? byte_c3_g3.................................................................................................... ... 59 10.7.43 qosc14 ? byte_c4_g3.................................................................................................... ... 59 10.7.44 qosc15 ? byte_c5_g3.................................................................................................... ... 59 10.7.45 qosc16 ? byte_c6_g3.................................................................................................... ... 59 10.7.46 qosc17 ? byte_c7_g3.................................................................................................... ... 59
data sheet MVTX2803Ag semicmf.xxx v 10.7.47 qosc18 ? byte_c2_g4 .................................................................................................... .........60 10.7.48 qosc019 ? byte_c3_g4 ................................................................................................... ........60 10.7.49 qosc1a ? byte_c4_g4 .................................................................................................... .........60 10.7.50 qosc1b ? byte_c5_g4 .................................................................................................... .........60 10.7.51 qosc1c ? byte_c6_g4 .................................................................................................... .........60 10.7.52 qosc1d? byte_c7_g4 ..................................................................................................... .........61 10.7.53 qosc1e? byte_c2_g5 ..................................................................................................... .........61 10.7.54 qosc1f ? byte_c3_g5 .................................................................................................... .........61 10.7.55 qosc20 ? byte_c4_g5 .................................................................................................... .........61 10.7.56 qosc21 ? byte_c5_g5 .................................................................................................... .........61 10.7.57 qosc22 ? byte_c6_g5 .................................................................................................... .........62 10.7.58 qosc23 ? byte_c7_g5 .................................................................................................... .........62 10.7.59 qosc24 ? byte_c2_g6 .................................................................................................... .........62 10.7.60 qosc25 ? byte_c3_g6 .................................................................................................... .........62 10.7.61 qosc26 ? byte_c4_g6 .................................................................................................... .........63 10.7.62 qosc27 ? byte_c5_g6 .................................................................................................... .........63 10.7.63 qosc28 ? byte_c6_g6 .................................................................................................... .........63 10.7.64 qosc29 ? byte_c7_g6 .................................................................................................... .........63 10.7.65 qosc2a ? byte_c2_g7 .................................................................................................... .........63 10.7.66 qosc2b ? byte_c3_g7 .................................................................................................... .........64 10.7.67 qosc2c ? byte_c4_g7 .................................................................................................... .........64 10.7.68 qosc2d ? byte_c5_g7 .................................................................................................... .........64 10.7.69 qosc2e ? byte_c6_g7 .................................................................................................... .........64 10.7.70 qosc2f ? byte_c7_g7 .................................................................................................... .........64 10.7.71 qosc30 ? byte_c01 ...................................................................................................... ............65 10.7.72 qosc31 ? byte_c02 ...................................................................................................... ............65 10.7.73 qosc32 ? byte_c03 ...................................................................................................... ............65 10.7.74 qosc33 ? credit_c0_g0 .................................................................................................. .......65 10.7.75 qosc34 ? credit_c1_g0 .................................................................................................. .......66 10.7.76 qosc35 ? credit_c2_g0 .................................................................................................. .......66 10.7.77 qosc36 ? credit_c3_g0 .................................................................................................. .......67 10.7.78 qosc37 ? credit_c4_g0 .................................................................................................. .......67 10.7.79 qosc38 ? credit_c5_g0 .................................................................................................. .......67 10.7.80 qosc39? credit_c6_g0 ................................................................................................... .......67 10.7.81 qosc3a? credit_c7_g0 ................................................................................................... .......67 10.7.82 qosc3b ? credit_c0_g1 .................................................................................................. .......67 10.7.83 qosc3c ? credit_c1_g1 .................................................................................................. .......68 10.7.84 qosc3d ? credit_c2_g1 .................................................................................................. .......69 10.7.85 qosc3e ? credit_c3_g1 .................................................................................................. .......69 10.7.86 qosc3f ? credit_c4_g1 .................................................................................................. .......69 10.7.87 qosc40 ? credit_c5_g1 .................................................................................................. .......69 10.7.88 qosc41? credit_c6_g1 ................................................................................................... .......69 10.7.89 qosc42? credit_c7_g1 ................................................................................................... .......69 10.7.90 qosc43 ? credit_c0_g2 .................................................................................................. .......70 10.7.91 qosc44 ? credit_c1_g2 .................................................................................................. .......70 10.7.92 qosc45 ? credit_c2_g2 .................................................................................................. .......71 10.7.93 qosc46 ? credit_c3_g2 .................................................................................................. .......71 10.7.94 qosc47 ? credit_c4_g2 .................................................................................................. .......71 10.7.95 qosc48 ? credit_c5_g2 .................................................................................................. .......71 10.7.96 qosc49? credit_c6_g2 ................................................................................................... .......72 10.7.97 qosc4a? credit_c7_g2 ................................................................................................... .......72 10.7.98 qosc4b ? credit_c0_g3 .................................................................................................. .......72 10.7.99 qosc4 ? credit_c1_g3 ................................................................................................... ........73 10.7.100 qosc4d ? credit_c2_g3 ................................................................................................. ......73
MVTX2803Ag data sheet vi semicmf.xxx 10.7.101 qosc4e ? credit_c3_g3 ................................................................................................ 7 3 10.7.102 qosc4f ? credit_c4_g3 ................................................................................................ 7 4 10.7.103 qosc50 ? credit_c5_g3................................................................................................. 74 10.7.104 qosc51? credit_c6_g3.................................................................................................. 74 10.7.105 qosc52? credit_c7_g3.................................................................................................. 74 10.7.106 qosc53 ? credit_c0_g4................................................................................................. 74 10.7.107 qosc54 ? credit_c1_g4................................................................................................. 75 10.7.108 qosc55 ? credit_c2_g4................................................................................................. 76 10.7.109 qosc56 ? credit_c3_g4................................................................................................. 76 10.7.110 qosc57 ? credit_c4_g4................................................................................................. 76 10.7.111 qosc58 ? credit_c5_g4................................................................................................. 76 10.7.112 qosc59? credit_c6_g4.................................................................................................. 76 10.7.113 qosc5a? credit_c7_g4 ................................................................................................. 7 6 10.7.114 qosc5b ? credit_c0_g5 ................................................................................................ 7 7 10.7.115 qosc5c ? credit_c1_g5 ................................................................................................ 7 7 10.7.116 qosc5d ? credit_c2_g5 ................................................................................................ 7 8 10.7.117 qosc5e ? credit_c3_g5 ................................................................................................ 7 8 10.7.118 qosc5f ? credit_c4_g5 ................................................................................................ 7 8 10.7.119 qosc60 ? credit_c5_g5................................................................................................. 78 10.7.120 qosc61? credit_c6_g5.................................................................................................. 79 10.7.121 qosc62? credit_c7_g5.................................................................................................. 79 10.7.122 qosc63 ? credit_c0_g6................................................................................................. 79 10.7.123 qosc64 ? credit_c1_g6................................................................................................. 80 10.7.124 qosc65 ? credit_c2_g6................................................................................................. 80 10.7.125 qosc66 ? credit_c3_g6................................................................................................. 80 10.7.126 qosc67 ? credit_c4_g6................................................................................................. 81 10.7.127 qosc68 ? credit_c5_g6................................................................................................. 81 10.7.128 qosc69? credit_c6_g6.................................................................................................. 81 10.7.129 qosc6a? credit_c7_g6 ................................................................................................. 8 1 10.7.130 qosc6b ? credit_c0_g7 ................................................................................................ 8 2 10.7.131 qosc6c ? credit_c1_g7 ................................................................................................ 8 2 10.7.132 qosc6d ? credit_c2_g7 ................................................................................................ 8 3 10.7.133 qosc6e ? credit_c3_g7 ................................................................................................ 8 3 10.7.134 qosc6f ? credit_c4_g7 ................................................................................................ 8 3 10.7.135 qosc70 ? credit_c5_g7................................................................................................. 83 10.7.136 qosc71? credit_c6_g7.................................................................................................. 84 10.7.137 qosc72? credit_c7_g7.................................................................................................. 84 10.7.138 qosc73 ? token_rate_g0............................................................................................. 84 10.7.139 qosc74 ? token_limit_g0 ............................................................................................. 84 10.7.140 qosc75 ? token_rate_g1............................................................................................. 84 10.7.141 qosc76 ? token_limit_g1 ............................................................................................. 85 10.7.142 qosc77 ? token_rate_g2............................................................................................. 85 10.7.143 qosc78 ? token_limit_g2 ............................................................................................. 85 10.7.144 qosc79 ? token_rate_g3............................................................................................. 85 10.7.145 qosc7a ? token_limit_g3............................................................................................. 86 10.7.146 qosc7b ? token_rate_g4 ............................................................................................ 86 10.7.147 qosc7c ? token_limit_g4 ............................................................................................ 86 10.7.148 qosc7d ? token_rate_g5 ............................................................................................ 86 10.7.149 qosc7e ? token_limit_g5............................................................................................. 86 10.7.150 qosc7f ? token_rate_g6 ............................................................................................ 87 10.7.151 qosc80 ? token_limit_g6 ............................................................................................. 87 10.7.152 qosc81 ? token_rate_g7............................................................................................. 87 10.7.153 qosc82 ? token_limit_g7 ............................................................................................. 87
data sheet MVTX2803Ag semicmf.xxx vii 10.7.154 rdrc0 ? wred rate control 0 ........................................................................................... ......88 10.7.155rdrc1 ? wred rate control 1 ............................................................................................ ......88 10.8 group 6 address - misc group .............................................................................................. ..................88 10.8.1 mii_op0 ? mii register option 0.............. ........................................................................... ............88 10.8.2 mii_op1 ? mii register option 1.............. ........................................................................... ............89 10.8.3 fen ? feature register .................................................................................................. .................89 10.8.4 miic0 ? mii command register 0 .......................................................................................... .........90 10.8.5 miic1 ? mii command register 1 .......................................................................................... .........90 10.8.6 miic2 ? mii command register 2 .......................................................................................... .........90 10.8.7 miic3 ? mii command register 3 .......................................................................................... .........90 10.8.8 miid0 ? mii data register 0 ............................................................................................. ...............91 10.8.9 miid1 ? mii data register 0 ............................................................................................. ...............91 10.8.10 led mode ? led control ....................... .......................................................................... .............91 10.8.11 device mode ............................................................................................................ ...................93 10.8.12 checksum - eeprom checksum............................................................................................. .93 10.8.13 led user ............................................................................................................... ........................94 10.8.14 leduser0 ............................................................................................................... .....................94 10.8.15 leduser1 ............................................................................................................... .....................94 10.8.16 leduser2/ledsig2....................................................................................................... .............95 10.8.17 eduser3/ledsig3........................................................................................................ ..............95 10.8.18 leduser4/ledsig4....................................................................................................... .............96 10.8.19 leduser5/ledsig5....................................................................................................... .............97 10.8.20 leduser6/ledsig6....................................................................................................... .............97 10.8.21 leduser7/ledsig1_0..................................................................................................... ...........98 10.8.22 miinp0 ? mii next page data register 0 . ................................................................................ .....99 10.8.23 miinp1 ? mii next page data register 1 . ................................................................................ .....99 10.9 group f address - cpu access group........................................................................................ .............99 10.9.1 gcr-global control register ............................................................................................. .............99 10.9.2 dcr-device status and signature register ................................................................................ ..100 10.9.3 dcr01-giga port status .................................................................................................. ..............100 10.9.4 dcr23-giga port status .................................................................................................. ..............101 10.9.5 dcr45-giga port status .................................................................................................. ..............101 10.9.6 dcr67-giga port status .................................................................................................. ..............102 10.9.7 dpst ? device port status register ...................................................................................... .......103 10.9.8 dtst ? data read back register .......................................................................................... .......103 11.0 bga and ball signal de scription......... ................. ................ .............. .............. ........... 104 11.1 bga views ................................................................................................................. .............................104 11.2 power and ground distribution ............................................................................................. ..................105 11.3 ball- signal descriptions ................................................................................................. ........................106 11.4 ball signal name.......................................................................................................... ...........................117 11.5 ac/dc timing ............................................................................................................ ...........................123 11.5.1 absolute maximum ratings ................................................................................................ ...........123 11.5.2 dc electrical characteristics ........................................................................................... ..............123 11.5.3 recommended operation conditions........................................................................................ ....123 11.6 local frame buffer zbt sram memory interfac e.............................................................................. ....124 11.6.1 local zbt sram memory interface a:...................................................................................... ....124 11.6.2 local zbt sram memory interface b:...................................................................................... ....125 11.7 local switch databa se sbram memory interface ................... ........................................................... ...126 11.7.1 local sbram memory interface: ........................................................................................... .......126 11.8 ac characteristics........................................................................................................ ...........................127 11.8.1 media independent interface ............................................................................................. ............127 11.8.2 gigabit media independent interface..................................................................................... ........128 11.8.3 pcs interface ........................................................................................................... .....................129
MVTX2803Ag data sheet viii semicmf.xxx 11.8.4 led interface ........................................................................................................... ...............130 11.8.5 mdio input setup and hold timing ........................................................................................ 131 11.8.6 i 2 c input setup timing........................................................................................................... .131 11.8.7 serial interface setup timing................... ........................................................................ .......132
data sheet MVTX2803Ag semicmf.xxx ix list of figures figure 1 - MVTX2803Ag block diagram ........................................................................................... .......................1 figure 2 - data transfer format for i 2 c interface .....................................................................................................6 figure 3 - MVTX2803Ag sram interface block diagram (d mas for gigabit ports) ...............................................9 figure 4 - buffer partition scheme used in the mv tx2803ag ..................................................................... .........16 figure 5 - timing diagram for serial mode in led interface .................................................................... ...............19 figure 6 - local memory interface ? input setup and ho ld timing ............................................................... ..........124 figure 7 - ocal memory interface - output valid delay timing .................................................................. .............124 figure 8 - local memory interface ? input setup and ho ld timing ............................................................... ..........125 figure 9 - local memory interface - output valid delay timing ................................................................. ............125 figure 10 - local memory in terface ? input setup and hold timing .............................................................. .........126 figure 11 - local memory in terface - output valid delay timing ... ............................................................. ...........126 figure 12 - ac characteristics ? me dia independent interface ................................................................... ......... 127 figure 13 - ac characteristics ? media independent interface ................................................................. ..........127 figure 14 - ac characteristics- gmii .......................................................................................... ..........................128 figure 15 - ac characteristics ? gi gabit media independent interface .......................................................... .....128 figure 16 - ac characteristics ? pcs interface ................................................................................ ...................129 figure 17 - ac characteristics ? pcs interface ................................................................................. .................. 129 figure 18 - ac characteristics ? led interface ................................................................................ ....................130 figure 19 - mdio input setup and hold timing . ................................................................................. .................131 figure 20 - mdio output delay timing .......................................................................................... ......................131 figure 21 - i 2 c input setup timing .......................................................................................................... .............131 figure 22 - i 2 c output delay timing ......................................................................................................... ...........131 figure 23 - serial interface setup timing ........ ............................................................................. ........................132 figure 24 - serial interface output delay timing .............................................................................. ...................132
MVTX2803Ag data sheet x semicmf.xxx
data sheet MVTX2803Ag xi semicmf.019 list of tables table 1 - two-dimensional world traffic ........... ............................................................................ ....................... 12 table 2 - four qos configurations per port. ...... ............................................................................. ...................... 13 table 3 - wred dropping scheme ................................................................................................. ..................... 14 table 4 - mapping betw een MVTX2803Ag and ietf diffserv classes for gigabit ports .................................... 17 table 5 - MVTX2803Ag features enabling ietf diffser v standards ................................................................ .. 18 table 6 - ac characteristics ? local frame buffer zbt- sram memory interface a .......................................... 125 table 7 - local frame buffer zbt-sram memory interface b ...................................................................... ...... 126 table 8 - ac characteristics ? local switch database sbram memory interface ............................................ 127 table 9 - ac characteristics ? media independent interface .................................................................... ......... 128 table 10 - ac characteristics ? gigabit media independent interface ........................................................... .... 129 table 11 - ac characteristics ? pcs interface ................................................................................. .................. 130 table 12 - ac characteristics ? led interface .. ............................................................................... .................. 130 table 13 - mdio timing ........................................................................................................ .............................. 131 table 14 - i 2 c timing ...................................................................................................................... .................... 132 table 15 - serial interface timing ............................................................................................ ........................... 132
MVTX2803Ag data sheet semicmf.019 xii
data sheet MVTX2803Ag 5 semicmf.019 1.0 block functionality 1.1 frame data buffe r (fdb) interfaces the fdb interface supports pipelined zbt-sram memory at 133 mhz. to ensure a non-blocking switch, two memory domains are required. each domain has a 64-bit wide memory bus. at 133 mhz, the aggregate memory bandwidth is 17 gbps, which is enough to support 8 gigabit ports at full wire speed switching. a patent pending scheme is used to access the fdb memory. each slot has one tick to read or write 8 bytes. 1.2 switch database (sdb) interface a pipelined synchronous burst sram (sbram) memory is used to store the switch database information including mac table. search engine accesses the s witch database via sdb interface. the sdb bus has 32- bit wide bus at 133mhz. 1.3 gmii/pcs mac module (gmac) the gmii/pcs media access control (mac) module prov ides the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). the MVTX2803Ag has two interfaces, gmii or pcs. the mac of the MVTX2803Ag meets the ieee 802.3z specification and supports the mii interface. it is able to operate 10m/100m/1g in full duplex mode with a back pressure/flow control mechanism. it has the options to insert source addr ess/crc/vlan id to each frame. the gmii/pcs module also supports hot plug detection. 1.4 frame engine the main function of the frame engine is to forward a frame to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request which is sent to the search engine, to resolve the destinatio n port. the arriving frame is moved to the fdb. after receiving a switch response from the search engi ne, the frame engine performs transmission scheduling based on the frame?s priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.5 search engine the search engine resolves the frame?s destination por t or ports according to the destination mac address (l2) by searching the database. it also performs mac learning, priority assignm ent, and trunking functions. 1.6 led interface the led interface can be operated in a serial mode or a parallel mode. in the serial mode, the led interface uses 3 pins for carrying 8 port status signals. in the parallel mode, the interface can drive leds by 8 status pins. the led port is shared with bootstrap pins. in or der to avoid error when reading the bootstraps, a buffer must be used to isolate the led circuitry from the bo otstrap pins during bootstrap cycle (the bootstrap pins are sampled at the rising edge of the reset). 1.7 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contains the control information of the associated frame stored in the fdb, e.g. frame size, read/write pointer, transmission priority, etc. ? mct link table - the mct link table stores the link ed list of mct entries that have collisions in the external mac table. 2.0 system configuration the MVTX2803Ag can be configured by eeprom (24c02 or compatible) via an i 2 c interface at boot time, or via a synchronous serial interface during operation. 2.1 i 2 c interface the i 2 c interface uses two bus lines, a serial data line (s da) and a serial clock line (scl). the scl carries the control signals that facilitate the transfer of informat ion from the eeprom to the switch. data transfer is a
MVTX2803Ag data sheet semicmf.019 6 bidirectional 8-bit serial at a rate of 50 kbps. data transfer is performed between master and slave ic using a request / acknowledgment style of protocol. the mast er ic generates the timing signals and terminates data transfer. the figure below shows the data transfer format. figure 2 - data transfer format for i 2 c interface 2.1.1 start condition generated by the master, the MVTX2803Ag. the bus is considered to be busy after the start condition is generated. the start condition occurs if, while the scl li ne is high, there is a high-to-low transition of the sda. other than in the start condition (and stop condition), the data on the sda line must be stable during the high period of scl. the high or low state of sda can only change when scl is low . in addition, when the i 2 c bus is free, both lines are high. 2.1.2 address the first byte after the start condition determines which slave the master will select. the slave in our case is the eeprom. the first seven bits of the first data byte make up the slave address. 2.1.3 data direction the eighth bit in the first byte after the start condition determines the direction (r/w) of the message. a master transmitter sets this bit to w; a master receiver sets this bit to r. 2.1.4 acknowledgment like all clock pulses, the master generates the ackn owledgment-related clock pulse. however, the transmitter releases the sda (high) during the acknowledgment clock pulse. furthermore , the receiver must pull down the sda during the acknowledge pulse so that it remains st able low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte , then the master generates a stop condition and aborts the transfer. if a master receiver does not acknowledge after any byte , then the slave transmitter must release the sda line to let the master generate the stop condition. 2.1.5 data after the first byte containing the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb-first. 2.1.6 stop condition generated by the master, the MVTX2803Ag. the bus is considered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda. the i 2 c interface serves the function of configuring the MVTX2803Ag at boot time. the master is the MVTX2803Ag, and the slave is the eeprom memory. 2.2 synchronous serial interface the synchronous serial interface serves t he function of configuring the MVTX2803Ag not at boot time but via a pc. the pc serves as master and the MVTX2803Ag serv es as slave. the protocol for the synchronous serial interface is nearly identical to the i 2 c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged MVTX2803Ag uses a synchronous serial inte rface to program the internal registers. to reduce the number of signals required, the register add ress, command and data are shifted in serially through the ps_do pin. ps_strobe- pin is used as the shift clock. ps_di- pin is used as data return path. start slave address r/w ack data 1 (8 bits) ack data 2 (8 bits) ack data m (8 bits) ack stop
data sheet MVTX2803Ag 7 semicmf.019 each command consists of four parts. ?start pulse ? register address ? read or write command ? data to be written or read back any command can be aborted in the middle by sending an abort pulse to the MVTX2803Ag. a start command is detected when ps_do is sampl ed high at ps_strobe - leading edge, and ps_do is sampled low when strobe- falls. an abort command is detected when ps_do is sample d low at ps_strobe - leading edge, and ps_do is sampled high when ps_strobe - falls. 2.2.1 write command 2.2.2 read command all registers in the MVTX2803Ag can be modifi ed through this synchronous serial interface. 3.0 data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). a fcb handle will always be availabl e, because of advance buffer reservations. the memory (zbt-sram) interface is two 64-bit buses , connected to two zbt-sram domains, a and b. the receive (rxdma) is responsible for multiplexing the dat a and the address. on a port?s ?turn,? the rxdma will move 8 bytes (or up to the end-of-frame) from the port?s associated receive fifo (rxfifo) into memory (frame data buffer, or fdb). once an entire frame has been moved to the fdb, and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing the source and destination mac addresses of the frame. the search engine places a switch response in the switch response queue of the frame engine when done. among other information, the s earch engine will have resolved the destination port of the frame and will have determined that the frame is unicast. ps-strobe- ps_d0 start address command data w a0 a1 a2 ... a9 a10 a11 d0 d1 d2 d3 d4 d5 d6 d7 2 extra clocks after last transfer ps-strobe- ps_d0 start address command data r a0 a1 a2 ... a9 a10 a11 ps_di d0 d1 d2 d3 d4 d5 d6 d7
MVTX2803Ag data sheet semicmf.019 8 after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destinati on port that it has a frame to forward. but first, the txq manager has to decide whether or not to drop the frame, based on global fdb reservations and usage, as well as txq occupancy at the destination. if the frame is not dropped, then the txq manager links the frame?s fcb to the correct per-port-per-class txq. unicast txq?s are link ed lists of transmission jobs, represented by their associated frames? fcb?s. there is one linked list for each transmission class for each port. there are 8 classes for each of the 8 gigabit ports ? a total of 32 unicast queues. the txq manager is responsible for scheduling transmi ssion among the queues representing different classes for a port. when the port control module determines t hat there is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues for that port, using a zarlink semiconductor scheduling algorithm. at the transmit end, each of the 8 ports has time slot s devoted solely to reading data from memory at the address calculated by port control. the transmission dma (txdma) is responsible for multiplexing the data and the address. on a port?s turn, the txdma will move 8 bytes (or up to the eof) from memory into the port?s associated txfifo. after reading the eof, the port control requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 3.2 multicast data frame forwarding after receiving the switch response, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utilization and re servations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet?s destinations. if so , then the frame is dropped at some destinations but not others, and the fcb is not released. if the frame is not dropped at a particular destinat ion port, then the txq manager formats an entry in the multicast queue for that port and class. multicast queue s are physical queues (unlike the linked lists for unicast frames). there are 4 multicast queues for each of the 8 gigabit ports. there is one multicast queue for every two unicast classes. during scheduling, the txq manager treats the unica st queue and the multicast queue of the same class as one logical queue. the port control requests a fcb release only after the eof for the multicast frame has been read by all ports to which the frame is destined. 4.0 memory interface 4.1 overview figure 3 illustrates the first part of the zbt-sram interface for the MVTX2803Ag. as shown, two zbt-sram banks, a and b, are used, with a 64-bit bus connected to each. each dma can read and write from both bank a and bank b. during each tick, two memory operations wil l take place in parallel ? one for bank a, and one for bank b. because the clock frequency is 133 mh z, the total memory bandwidth is 128 bits 133 mhz = 17 gbps, for frame data buffer (fdb) access. in addition, the figure shows that the 8 gigabit ports are ac tually grouped into sets of 4. if txdma 0 is using bank b during a given memory slot, th en txdma?s 1-3 will never be using bank a during this same slot. as a result, txdma?s 0-3 can share the same bank selector.
data sheet MVTX2803Ag 9 semicmf.019 figure 3 - MVTX2803Ag sram interface block diagram (dmas for gigabit ports) 4.2 detailed memory information because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from memory. the first 8-byte granule gets written to bank a, the second 8-byte granule gets written to bank b, and so on in alternating fashion. when reading frames from memory, the same procedure is followed, first from a, then from b, and so on. the reading and writing from alternating memory bank s can be performed with minimal waste of memory bandwidth. for any speed port, in the worst case, a 1-byte-long eof granule gets written to bank a. this means that a 7-byte segment of bank a bandwidth is idle , and furthermore, the next 8-byte segment of bank b bandwidth is idle, because the first 8 bytes of the next frame will be written to bank a, not b. this scenario results in a maximum 15 bytes of waste per frame, wh ich is always acceptable because the interframe gap is 20 bytes. search engine data is written to both banks in parall el. in this way, a search engine read operation could be performed by either bank at any time without a problem. 5.0 search engine 5.1 search engine overview the MVTX2803Ag search engine is optimized for high throughput searching, with enhanced features to support: ? up to 64k mac addresses ? 4 groups of port trunking ? traffic classification into 8 transmi ssion priorities, and 2 drop precedence levels 5.2 basic flow shortly after a frame enters the MVTX2803Ag and is writt en to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the sear ch engine. the switch request consists of the first 64 bytes of the frame, which contain all the necessary in formation for the search engine to perform its task. when the search engine is done, it writes to the switch response queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted are the source and destination mac addresses, the transmission and discard priorities and whether the frame is unicast or multicast. requests are sent to the external sram switch database to locate the associated entries in the external mct table. zbt-sram bank a zbt-sram bank b txdma 0-1 txdma 2-3 txdma 4-5 txdma 6-7 rxdma 0-1 rxdma 2-3 rxdma 4-5 rxdma 6-7
MVTX2803Ag data sheet semicmf.019 10 when all the information has been collected from exte rnal sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries, ot her than the first of each linked list, are maintained internal to the chip. if the desired mac address is still not found, then the result is either learning (source mac address unknown) or flooding (destination mac address unknown). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the frame be transmitted? this is easily computed using a hash of the source and destination mac addresses. when all the information is compiled, the swit ch response is generated, as stated earlier. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source mac address and destination mac address searching. as indicated earlier, if a match is not found, then the nex t entry in the linked list must be ex amined, and so on until a match is found or the end of the list is reached. in port based vlan mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing port. the bitmap is not dynamic. port s cannot enter and exit groups dynamically. the mac search block is also responsible for updat ing the source mac address timestamp, used for aging. 5.3.2 learning the learning module learns new mac addresses and per forms port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. learning and port change will be performed based on memory slot availability only. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a pr ogrammable "age out" time interval. as indicated earlier, the search module updates the source mac a ddress and vlan port association timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from the table. 5.3.4 data structure the mct data structure is used when searching for mac addresses. the structure is maintained by hardware in the search engine. the database is essentially a hash table, with collisions resolved by chaining. the database is partial external, and partial internal, as de scribed earlier: the first mct entry of each linked list is always located in the external sram, and the subsequent mct?s are located internally. 6.0 frame engine 6.1 data forwarding summary data enters the device at the rxmac, the rxdma will move the data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjunction with the scheme for the sram interface. ? a switch request is sent to the search engine . the search engine processes the switch request. ? a switch response is sent back to the frame en gine and indicates whether the frame is unicast or multicast, and its destination port or ports. ? a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling request, the device will format an entry in the appropriate transmission scheduling queue (txsch q) or queues. there are 8 txsch queues for each gigabit port, one for each priority. creation of a queue entry either involves linking a new jo b to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. ? when the port is ready to accept the next frame, t he txq manager will get the head-of-line (hol) entry of one of the txsch qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). the unicast linked list and the multicas t queue for the same port-class pair are treated as one logical queue.
data sheet MVTX2803Ag 11 semicmf.019 ? the txdma will pull frame data from the memory and fo rward it granule-by-granule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of each of the modules of the MVTX2803Ag frame engine. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming frames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enforcing buffer reservations and limits. the default values can be determined by referring to chapter 8. in addition, the fcb manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct txsch q. the buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register fcbat. 6.2.2 rx interface the rx interface is mainly responsible for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an end of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 txq manager first, the txq manager checks the per-class queue stat us and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. if the decision is not to drop, the txq manager requests that the fcb manager li nk the unicast frame?s fcb to the correct per-port- per-class txq. if multicast, the txq manager writes to the multicast queue for that port and class. the txq manager can also trigger source port flow control for the incoming frame?s source if that port is flow control enabled. second, the txq manager handles transmissi on scheduling; it schedules transmission among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read addr ess for the frame currently being transmitted. it also writes start of frame information and an end of frame fl ag to the mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. 7.0 quality of service and flow control 7.1 model quality of service (qos) is an all-encompassing term fo r which different people have different interpretations. in this chapter, quality of service assurances means the al location of chip resources so as to meet the latency and bandwidth requirements associated with each tr affic class. there is nothing presupposed about the offered traffic pattern. if the traffic load is light, then ens uring quality of service is straightforward. but if the traffic load is heavy, the MVTX2803Ag must intelligently al locate resources so as to assure quality of service for high priority data. the network manager must assign importance for the applic ation types, such as voice, file transfer, or web browsing. the manager can then subdivide the applicatio ns into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per class. sometimes it may even reflect an estimate of the traffic mix offered to the switch, though this is not required.
MVTX2803Ag data sheet semicmf.019 12 the table below shows examples of qos applications with eight transmiss ion priorities, including best effort traffic for which no bandwidth or latency assurances are provided. table 1 - two-dimensional world traffic it is possible that a class of traffic may attempt to monopolize system resources by sending data at a rate in excess of the contractually assured bandwidth for that cl ass. a well-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast, a mis behaving class offers traffic that exceeds the agreed rate. a misbehaving class is formed from an aggregation of misbehaving microflows. to achieve high link utilization, a misbehaving class is allowed to use any id le bandwidth. however, the quality of service (qos) received by well-behaved classes must never suffer. as table 1 illustrates, each traffic class may have it s own distinct properties and applications. as shown, classes may receive bandwidth assurances or latency bounds. in the example, p7, the highest transmission class, requires that all frames be transmitted within 0.2 ms, and receives 30% of the 1 gbps of bandwidth at that port. best-effort (p1-p0) traffic forms a lower tier of se rvice that only receives bandwidth when none of the other classes have any traffic to offer. in addition, each transmission class has two subcla sses, high-drop and low-drop. well-behaved users should not lose packets. but poorly behaved users ? users who send data at too high a rate ? will encounter frame loss, and the first to be discarded will be high-drop. of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped as well. table 1 shows that different types of applications may be placed in different boxes in the traffic table. for example, web search may fit into the category of high-lo ss, high-latency-tolerant traffic, whereas voip fits into the category of low-loss, low-latency traffic. class example assured bandwidth (user defined) low drop subclass (if class is oversubscribed, these packets are the last to be dropped) high drop subclass (if class is oversubscribed, these packets are the first to be dropped) highest transmission priorities, p7 latency < 200 s 300 mbps sample application: control information highest transmission priorities, p6 latency < 200 s 200 mbps sample applications: phone calls; circuit emulation sample application: training video; other multimedia middle transmission priorities, p5 latency < 400 s 125 mbps sample application: interactive activities sample application: non- critical interactive activities middle transmission priorities, p4 latency < 800 s 250 mbps sample application: web business low transmission priorities, p3 latency < 1600 s 80 mbps sample application: file backups low transmission priorities, p2 latency < 3200 s 45 mbps sample application: email sample application: web research best effort, p1-p0 ? sample application: casual web browsing total 1 gbps
data sheet MVTX2803Ag 13 semicmf.019 7.2 four qos configurations there are four basic pieces to qos scheduling in the mv tx2803ag: strict priority (sp), delay bound, weighted fair queuing (wfq), and best effort (be). using these four pieces, there are four different modes of operation, as shown in table 2. table 2- four qos configurations per port. the default configuration is six delay-bounded queues and two best-effort queues. the delay bounds per class are 0.16 ms for p7 and p6, 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. best effort traffic is only served when there is no delay-bounded traffic to be served. p1 has strict priority over p0. there is a second configuration in which there ar e two strict priority queues, four delay bounded queues, and two best effort queues. the delay bounds per class are 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. if the user is to choose this configur ation, it is important that p7-p6 (sp) traffic be either policed or implicitly bounded (e.g. if the incoming sp traf fic is very light and predictably patterned). strict priority traffic, if not admission-controlled at a prior stage to the MVTX2803Ag, can have an adverse effect on all other classes? performance. p7 and p6 are both sp classes, and p7 has strict priority over p6. the third configuration contains two strict priority queues and six queues receiving a bandwidth partition via wfq. as in the second configuration, strict pr iority traffic needs to be carefully controlled. in the fourth configuration, all queues are served using a wfq service discipline 7.3 delay bound in the absence of a sophisticated qos server and si gnaling protocol, the MVTX2803Ag may not be assured of the mix of incoming traffic ahead of time. to cope with this uncertainty, the delay assurance algorithm dynamically adjusts its scheduling and dropping criter ia, guided by the queue occupancies and the due dates of their head-of-line (hol) frames. as a result, latenc y bounds are assured for all admitted frames with high confidence, even in the presence of system-wide c ongestion. the algorithm identifies misbehaving classes and intelligently discards frames at no detriment to we ll-behaved classes. the algorithm also differentiates between high-drop and low-drop traffic with a wei ghted random early drop (wred) approach. random early dropping prevents congestion by randomly dropping a per centage of high-drop frames even before the chip?s buffers are completely full, while still largely sparin g low-drop frames. this allows high-drop frames to be discarded early, as a sacrifice for future low-drop fr ames. finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 strict priority and best effort when strict priority is part of t he scheduling algorithm, if a queue has even one frame to transmit, it goes first. two of the four qos configurations include strict priority queues. the goal is for strict priority classes to be used for ietf expedited forwarding (ef), where perform ance guarantees are required. as indicated, it is important that strict priority traf fic be either policed or implicitly bound ed, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. two of the four qos configurations include best effort queues. the goal is for best effort classes to be used for non-essential traffic, because there are no assurances about best effort performance. however, in a typical network setting, much best effort traffic will be transmitted, and with an adequate degree of expediency. p7 p6 p5 p4 p3 p2 p1 p0 op1 ( default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq
MVTX2803Ag data sheet semicmf.019 14 because there is not any delay assurances for best effort traffic, enforcement of latency by dropping best effort traffic is not provided. furthermore, because it is assumed t hat strict priority traffic is carefully controlled before entering the MVTX2803Ag, a fair bandwidth partition by dropping strict priority traffic is not enforced. to summarize, dropping to enforce quality of service (i.e. ban dwidth or delay) does not apply to strict priority or best effort queues. it only drops frames from best effo rt and strict priority queues when global buffer resources become scarce. 7.5 weighted fair queuing in some environments ? for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential - wfq may be preferable to a delay-bounded scheduling discipline. the MVTX2803Ag provides the user with a wfq option with the understanding that delay assurances cannot be provided if the incoming traffi c pattern is uncontrolled. the user sets eight wfq "weights" such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though frame latency is not assured, the MVTX2803Ag still retains a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. as before, when strict priority is combined with wfq, t here are no special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. however, there is indeed drop frames from sp queues for global buffer management purposes. in addition, queues p1 and p0 are treated as best effort from a dropping perspective , though they still are assured a percentage of bandwidth from a wfq scheduling perspective. what this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 shaper although traffic shaping is not a primary function of the MVTX2803Ag, the chip does implement a shaper for expedited forwarding (ef). the goal in shaping is to control the peak and average rate of traffic exiting the MVTX2803Ag. shaping is limited to class p6 (the second hi ghest priority). this means that class p6 will be the class used for ef traffic. (by contrast, assume class p7 will be used for control packets only.) if shaping is enabled for p6, then p6 traffic must be scheduled using stri ct priority. with reference to table 4, only the middle two qos configurations may be used. peak rate is set using a programmable whole number, no greater than 64 (register qos-credit_c6_gn). for example, if the setting is 32, then the peak rate for shaped traffic is 32/64 1000 mbps = 500 mbps. average rate is also a programmable whole number, no greater than 64, and no greater than the peak rate. for example, if the setting is 16, then the average rate for shaped traffic is 16/64 1000 mbps = 250 mbps. as a consequence of the above settings in the example, shaped traffic will exit the MVTX2803Ag at a rate always less than 500 mbps, and averaging no greater than 250 mbps. also, when shaping is enabled, it is possible for a p6 queu e to explode in length if fed by a greedy source. the reason is that a shaper is by definition not work-con serving; that is, it may hold back from sending a packet even if the line is idle. though there is global resource management, nothing is done to prevent this situation locally. this assumes sp traffic is policed at a prior stage to the MVTX2803Ag. 7.7 wred drop threshold management support to avoid congestion, the weighted random early detecti on (wred) logic drops packets according to specified parameters. the following table summari zes the behavior of the wred logic. table 3- wred dropping scheme p7 p6 p5 p4 p3 p2 high drop low drop level 1 n 240 |p7| a kb |p6| b kb |p5| c kb |p4| d kb |p3| e kb |p2| f kb x% 0% level 2 n 280 y% z% level 3 n 320 100% 100%
data sheet MVTX2803Ag 15 semicmf.019 in the table, |px| is the byte count in queue px. t he wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the priority queues. if delay bound scheduling is used, n equals 16|p7| + 16|p6| + 8|p5| + 4|p4| + 2|p3| + |p2|. if wfq scheduling is used, n equals |p7| + |p6| + |p5| + |p4| + |p3| + |p2|. each drop level has defined high-drop and low-drop percentages, which indicate the percentage of high-drop and low-drop packets that will be dropped at that level. the x, y, and z percent parameters can be programmed using the registers rd rc0 and rdrc1. parameters a-f are the byte count thresholds for each priority queue, and are also programmable. when using delay bound scheduling, the values selected for a-f also control the approximat e bandwidth partition among the traffic classes; see application note. 7.8 buffer management because the number of frame data buffer (fdb) slot s is a scarce resource, and because it is desirable to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, the concept of buffer management was produced into the MVTX2803Ag. the buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, (see figure 4). as shown in the figure, the fdb pool is divided into several parts. a reserved region for temporary frames stores frames prior to receiving a switch response . such a temporary region is necessary, because when the frame first enters the MVTX2803Ag, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. this ens ures that every frame can be received first before subjecting it to the frame dr op discipline after classifying. six reserved sections, one for each of the highest six prio rity classes, ensure a programmable number of fdb slots per class. the lowest two classes do not receive any buffer reservation. another segment of the fdb reserves space for each of t he 8 ports. these source port buffer reservations are programmable. these 8 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. in addition, there is a shared pool, which can store any type of frame. the registers related to the buffer management logic are: ? prg- port reservation for gigabit ports ? sfcb- share fcb size ? c2rs- class 2 reserved size ? c3rs- class 3 reserved size ? c4rs- class 4 reserved size ? c5rs- class 5 reserved size ? c6rs- class 6 reserved size ? c7rs- class 7 reserved size
MVTX2803Ag data sheet semicmf.019 16 figure 4 - buffer partition scheme used in the MVTX2803Ag 7.8.1 dropping when buffers are scarce summarizing the two examples of local dr opping discussed earlier in this chapter: ? if a queue is a delay-bounded queue, we have a multilev el wred drop scheme, designed to control delay and partition bandwidth in case of congestion. ? if a queue is a wfq-scheduled queue, we have a mu ltilevel wred drop schem e, designed to prevent congestion. in addition to these reasons for dropping, the mvtx 2803ag also drops frames when global buffer space becomes scarce. the function of buffer management is to ensure that such droppings cause as little blocking as possible. 7.9 MVTX2803Ag flow control basics because frame loss is unacceptable for some applica tions, the MVTX2803Ag provides a flow control option. when flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port, sending a packet to this switch, to temporarily hold off. while flow control offers the clear benefit of no packet lo ss, it also introduces a problem for quality of service. when a source port receives an ethernet flow control si gnal, all microflows originating at that port, well- behaved or not, are halted. a single packet destined for a congested output can block other packets destined for uncongested outputs. the resulting head-of-line bl ocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. in the MVTX2803Ag, each source port can independent ly have flow control enabl ed or disabled. for flow control enabled ports, by default all frames are treated as lowest priority during tr ansmission scheduling. this is done so that those frames are not exposed to the wred dropping scheme. frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priority. what this means is that if flow control is enabled for a given source port, then it ca n guarantee that no packets originating from that port will be lost, but at the possible expense of minimu m bandwidth or maximum delay assurances. in addition, these "downgraded" frames may only use the shared pool or the per-source reserved pool in the fdb; frames from flow control enabled sources may not use rese rved fdb slots for the highest six classes (p2-p7). the MVTX2803Ag does provide a system-wide option of permitting normal qos scheduling (and buffer use) for frames originating from flow control enabled ports. when this programmable option is active, it is possible temporary reservation r tmp per-source reservations 8-r 1g per-class r p7 , r p6 ,...r p2 shared pool s reservations
data sheet MVTX2803Ag 17 semicmf.019 that some packets may be dropped, even though flow cont rol is on. the reason is that intelligent packet dropping is a major component of the MVTX2803A g?s approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.9.1 unicast flow control for unicast frames, flow control is triggered by so urce port resource availability. recall that the MVTX2803Ag?s buffer management scheme allocates a rese rved number of fdb slots for each source port. if a programmed number of a source port?s reserved fdb slots have been used, then flow control xoff is triggered. xon is triggered when a port is currently bei ng flow controlled, and all of that port?s reserved fdb slots have been released. note that the MVTX2803Ag?s per-source-port fdb reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.9.2 multicast flow control when port based vlan is not used, a global buffer count er (64 packets) triggers flow control for multicast frames. when the system exceeds a programmable threshol d of multicast packets, xoff is triggered. xon is triggered when the system returns below this threshol d. mcc register programs the threshold. when port based vlan is used, each vlan has a global buffer counter. in addition, each source port has an 8-bit port map record ing which port or ports of the multicast frame?s fanout were congested at the time xoff was triggered. all po rts are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy fall s below a fixed threshold. when all those ports that were originally marked as congested in the por t map have become uncongested, then xon is triggered, and the 8-bit vector is reset to zero. the MVTX2803Ag also provides the option of disabling vlan multicast flow control. note: if port flow control is on, qos performance will be affected. to determine the most efficient way to program, please refer to the qos application note. 7.10 mapping to ietf diffserv classes the mapping between priority classes discussed in this chapter and elsewhere is shown below. table 4- mapping between MVTX2803Ag and ietf diffserv classes for gigabit ports as the table illustrates, p7 is used solely for net work management (nm) frames. p6 is used for expedited forwarding service (ef). classes p2 through p5 corre spond to an assured forwarding (af) group of size 4. finally, p0 and p1 are two best effort (be) classes. MVTX2803Ag p7 p6 p5 p4 p3 p2 p1 p0 ietf nm ef af0 af1 af2 af3 be0 be1
MVTX2803Ag data sheet semicmf.019 18 features of the MVTX2803Ag that correspond to the requirements of their associated ietf classes are summarized in the following below. table 5- MVTX2803Ag features enabling ietf diffserv standards 8.0 port trunking 8.1 features and restrictions a port group (i.e. trunk) can include up to 8 physical ports, but all of the ports in a group must be in the same MVTX2803Ag. the MVTX2803Ag provides several pre-assigned trunk group options, containing as many as 4 ports per group, or alternatively, as many as 4 total groups. load distribution among the ports in a trunk for unica st is performed using hashing based on source mac address and destination mac address. the other options include source mac address only, destination mac address only. load distribution for multicast is performed similarly. if a vlan includes any of the ports in a trunk group, al l the ports in that trunk group should be in the same vlan member map. the MVTX2803Ag also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the MVTX2803Ag will automatically redistribute the traffic over to the remaining ports in the trunk in unmanaged mode. in managed mode, the software can perform similar tasks. 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status field says that the destination address found belongs to a trunk, then the group number is retrieved instead of the port number. in addition, if the source address belongs to a trunk, then the source port?s tr unk membership register is checked to determine if the address has moved. a hash key is used to determine the appropriate forw arding port, based on some combination of the source and destination mac addresses for the current packet. the search engine retrieves the vlan member ports from the vlan index table, whic h consists of 4k entries. the search engine retrieves the vlan member ports from the ingress port?s vlan map. based on the destination mac address, the search engine determines the egress port from the mct database. if the egress port is a member of a trunk group, the packet can be distributed to the other members of that trunk group. the vlan map is used to check whether the egress port is a member of the vlan, based on the ingress port. if it is a member, the packet is forwarded otherwise it is discarded. network management (nm) and expedited forwarding (ef) ? global buffer reservation for nm and ef ? shaper for ef traffic ? option of strict priority scheduling ? no dropping if admission controlled assured forwarding (af) ? four af classes ? programmable bandwidth partition, with option of wfq service ? option of delay-bounded service keeps delay under fixed levels even if not admission-controlled ? random early discard, with programmable levels ? global buffer reservation for each af class best effort (be) ? two be classes ? service only when other queues are idle means that qos not adversely affected ? random early discard, with programmable levels ? traffic from flow control enabled ports automatically classified as be
data sheet MVTX2803Ag 19 semicmf.019 8.3 multicast packet forwarding for multicast packet forwarding, the device must determi ne the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multic ast packets to the appropriate destination ports in a port trunking environment. ? determining one forwarding port per group. ? for multicast packets, all but one port per group, the forwarding port, must be excluded. 8.4 preventing multicast packets from looping back to the source trunk the search engine needs to prevent a multicast packet fr om sending to a port that is in the same trunk group with the source port. this is because, when selecting the primary forwarding port for each group, it does not take the source port into account. to prevent this, simply apply one additional filt er, so as to block that forwarding port for this multicast packet. 9.0 led interface 9.1 introduction the MVTX2803Ag led block provides tw o interfaces: a serial output channel, and a parallel time-division interface. the serial output channel provides port status information from the MVTX2803Ag chip in a continuous serial stream. this means that a low cost external device must be used to decode the serial data and to drive an led array for display. by contrast, the parallel time-divis ion interface supports a glueless led m odule. indeed, the parallel interface can directly drive low-current leds without any extra logic. the pin led_pm is used to select serial or parallel mode. for some led signals, the interface also provides a bl inking option. blinking ma y be enabled for led signals txd, rxd, col, and fc (to be described later). th e pin led_blink is used to enable blinking, and the blinking frequency is around 160 ms. 9.2 serial mode in serial mode, the following pins are utilized: ? led_synco ? a sync pulse that defines the boundary between status frames ? led_clko ? the clock signal ? led_do ? a continuous serial stream of data for all status leds that repeats once every frame time in each cycle (one frame of status information, or one sync pulse), 16 8 bits of data are transmitted on the led_do signal. the sequence of transmission of data bits is as shown in the figure below: figure 5 - timing diagram for serial mode in led interface p0 info p1 info p2 info p3 info p4 info p5 info p6 info p7 info u0 u1 u2 u3 u4 u5 u6 u7 le_synco le_do le_clko fc txd rxd lnk sp0 sp1 fdx col 07 6 5 4 3 2 1
MVTX2803Ag data sheet semicmf.019 20 the status bits shown in here are flow control (fc), transmitting data (txd), rece iving data (rxd), link up (lnk), speed (sp0 and sp1), full duplex (fdx), and coll ision (col). note that sp[1:0] is defined as 10 for 1 gbps, 01 for 100 mbps, and 00 for 10 mbps. also note that u0-u7 represent user-defined sub-fr ames in which additional status information may be embedded. we will see later that the MVTX2803Ag prov ides registers that can be written by the cpu to indicate this additional status in formation as it becomes available. 9.3 parallel mode in parallel mode, the following pins are utilized: ? led_port_sel[9:0] ? indicates which of the 8 gigabit port status bytes or 2 user-defined status bytes is being read out ? led_byteout_[7:0] ? provides 8 bits for 8 different port status indicators. note that these bits are active low. by default, the system is in parallel mode. in para llel mode, the 10 status bytes are scanned in a continuous loop, with one byte read out per clock cycle, and the appropriate port select bit asserted. 9.4 led control registers an led control register can be used for programming the led clock rate, sample hold time, and pattern in parallel mode. in addition, the MVTX2803Ag pr ovides 8 registers called leduser[7:0] fo r user-defined status bytes. during operation, the cpu can write values to these register s, which will be read out to the led interface output (serial or parallel). only leduser[1:0] are used in pa rallel mode. the content of the leduser registers will be sent out by the led serial shift logic, or in parallel mode, a byte at a time. because in parallel mode there are only two use r-defined registers, leduser[7:2] is shared with ledsig[7:2]. for ledsig[j], where j = 2, 3, ..., 6, the corresponding register is used for programming the led pin led_byteout_[j]. the format is as follows: bits [3:0] signal polarity: 0: do not invert polarity (high true) 1: invert polarity bits [7:4] signal select: 0: do not select 1: select the corresponding bit for j = 2, 3, 4, 5, the value of led_byteout_[j] equals the logical and of all selected bits. for j = 6, the value is equal to the logical or. therefore, the programmable ledsig[5:2] registers allow any conjunctive formula including any of the 4 status bits (col, fdx, sp1, sp0) or their negations to be sent to the led_byteout_[5:2] pins. similarly, the programmabl e ledsig[6] register allows any disjunctive formula including any of the 4 status bits or their negations to be sent to pin led_byteout_[6]. ledsig[7] is used for programming both led_byteout_[1 ] and led_byteout_[0]. as we will see, it has other functions as well. the format is as follows: 7 43 0 col fdx sp1 sp0 col fdx sp1 sp0 7 43 0 gp rxd txd fc p6 rxd txd fc
data sheet MVTX2803Ag 21 semicmf.019 10.0 register definition 10.1 MVTX2803Ag register description bits [7] ? global output polarity: this bit contro ls the output polarity of all led_byteout_ and led_port_sel pins. (default 0) 0: do not invert polarity (led_byteout_[7:0] are high activated; led_port_sel[9:0] are low activated) 1: invert polarity (led_byteout_[7:0] ar e low activated; led_port_sel[9:0] are high activated) bits [6:4] ? signal select: 0: do not select 1: select the corresponding bit ? the value of led_byteout_[1] equals the logical or of all selected bits. (default 110) bit [3] ? polarity contro l of led_byteout_[6] (default 0) 0: do not invert 1: invert bits [2:0] ? signal select: 0: do not select 1: select the corresponding bit ? the value of led_byteout_[0] equals the logical or of all selected bits. ( default 001) register description cpu addr (hex) r/w i 2 c addr (hex) default notes ethernet port control registers ? substitute [n] with port number (0..7) ecr1p?n? port control register 1 for port n (n=0-7) 000 + 2n r/w 000+2n c0 ecr2p?n? port control register 2 for port n (n=0-7) 001 + 2n r/w 001+2n 00 ecrmisc1 port control misc1 010 r/w 010 c0 ecrmisc2 port control misc 2 011 r/w 011 00 ggcontrol0 extra gigabit port control ? port 0,1 012 r/w n/a 00 ggcontrol1 extra gigabit port control ? port 2,3 013 r/w n/a 00 ggcontrol2 extra gigabit port control ? port 4,5 014 r/w n/a 00 ggcontrol3 extra gigabit port control ? port 6,7 015 r/w n/a 00 activelink active link status port 7:0 016 r/w n/a 00
MVTX2803Ag data sheet semicmf.019 22 vlan control registers ? substitute [n] with port number (0..8) avtcl vlan type code register low 100 r/w 012 00 avtch vlan type code register high 101 r/w 013 81 pvmap?n?_0 port ?n? configuration register 0 (n=0-8) 102 + 4n r/w 014+4n ff pvmap?n?_1 port ?n? configuration register 1 (n=0-8) 103 + 4n r/w 015+4n ef pvmap?n?_2 port ?n? configuration register 2 (n=0-8) 104 + 4n r/w 016+4n 00 pvmap?n?_3 port ?n? configuration register 3 (n=0-8) 105 + 4n r/w 017+4n 00 pvmode vlan operating mode 126 r/w 038 00 trunk control registers trunk0 trunk group 0 member 200 r/w na 00 trunk1 trunk group 1 member 201 r/w na 00 trunk2 trunk group 2 member 202 r/w na 00 trunk3 trunk group 3 member 203 r/w na 00 single_ring single ring port map 204 r/w na trunk_ring trunk ring port map 205 r/w na trunk_hash_mode trunk hash mode 206 r/w na 00 trunk0_mode trunk group 0 mode 207 r/w 039 00 trunk0_hash0 trunk group 0 hash 0, 1, 2 destination port 208 r/w na 08 trunk0_hash1 trunk group 0 hash 2, 3, 4, 5 destination port 209 r/w na 82 trunk0_hash2 trunk group 0 hash 5, 6, 7 destination port 20a r/w na 20 trunk0_hash3 trunk group 0 hash 8, 9, 10 destination port 20b r/w na 08 trunk0_hash4 trunk group 0 hash 10, 11, 12, 13 destination port 20c r/w na 82 trunk0_hash5 trunk group 0 hash 13, 14, 15 destination port 20d r/w na 20 trunk1_mode trunk group 1 mode 20e r/w 03a 00 trunk1_hash0 trunk group 1 hash 0, 1, 2 destination port 20f r/w na 08 register description cpu addr (hex) r/w i 2 c addr (hex) default notes
data sheet MVTX2803Ag 23 semicmf.019 trunk1_hash1 trunk group 1 hash 2, 3, 4, 5 destination port 210 r/w na 82 trunk1_hash2 trunk group 1 hash 5, 6, 7 destination port 211 r/w na 20 trunk1_hash3 trunk group 1 hash 8, 9, 10 destination port 212 r/w na 08 trunk1_hash4 trunk group 1 hash 10, 11, 12, 13 destination 213 r/w na 82 trunk1_hash5 trunk group 1 hash 13, 14, 15 destination 214 r/w na 20 trunk2_hash0 trunk group 2 hash 0, 1, 2 destination port 215 r/w na 2c trunk2_hash1 trunk group 2 hash 2, 3, 4, 5 destination port 216 r/w na cb trunk2_hash2 trunk group 2 hash 5, 6, 7 destination port 217 r/w na b2 trunk2_hash3 trunk group 2 hash 8, 9, 10 destination port 218 r/w na 2c trunk2_hash4 trunk group 2 hash 10, 11, 12, 13 destination port 219 r/w na cb trunk2_hash5 trunk group 2 hash 13, 14, 15 destination port 21a r/w na b2 trunk3_hash0 trunk group 3 hash 0, 1, 2 destination port 21b r/w na 2c trunk3_hash1 trunk group 3 hash 2, 3, 4, 5 destination port 21c r/w na cb trunk3_hash2 trunk group 3 hash 5, 6, 7 destination port 21d r/w na b2 trunk3_hash3 trunk group 3 hash 8, 9, 10 destination port 21e r/w na 2c trunk3_hash4 trunk group 3 hash 10, 11, 12, 13 destination port 21f r/w na bc trunk3_hash5 trunk group 3 hash 13, 14, 15 destination port 220 r/w na b2 multicast_hash00 multicas t hash result 0 mask bit[7:0] 221 r/w na ff multicast_hash01 multicas t hash result 1 mask bit[7:0] 222 r/w na ff multicast_hash02 multicas t hash result 2 mask bit[7:0] 223 r/w na ff register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2803Ag data sheet semicmf.019 24 multicast_hash03 multicas t hash result 3 mask bit[7:0] 224 r/w na ff multicast_hash04 multicas t hash result 4 mask bit[7:0] 225 r/w na ff multicast_hash05 multicas t hash result 5 mask bit[7:0] 226 r/w na ff multicast_hash06 multicas t hash result 6 mask bit[7:0] 227 r/w na ff multicast_hash07 multicas t hash result 7 mask bit[7:0] 228 r/w na ff multicast_hash08 multicas t hash result 8 mask bit[7:0] 229 r/w na ff multicast_hash09 multicas t hash result 9 mask bit[7:0] 22a r/w na fff multicast_hash10 multicast hash result 10 mask bit[7:0] 22b r/w na ff multicast_hash11 multicas t hash result 11 mask bit[7:0] 22c r/w na ff multicast_hash12 multicast hash result 12 mask bit[7:0] 22d r/w na ff multicast_hash13 multicast hash result 13 mask bit[7:0] 22e r/w na ff multicast_hash14 multicast hash result 14 mask bit[7:0] 22f r/w na ff multicast_hash15 multicast hash result 15 mask bit[7:0] 230 r/w na ff multicast_hashml multicast hash bit[8] for result 7-0 231 r/w na ff multicast hashmh multicast hash bit[8] for result 15-8 232 r/w na ff cpu port configuration mac0 cpu mac address byte 0 300 r/w na 00 mac1 cpu mac address byte 1 301 r/w na 00 mac2 cpu mac address byte 2 302 r/w na 00 mac3 cpu mac address byte 3 303 r/w na 00 mac4 cpu mac address byte 4 304 r/w na 00 mac5 cpu mac address byte 5 305 r/w na 00 int_mask0 interrupt mask 0 306 r/w na ff int_mask1 interrupt mask 1 307 r/w na ff register description cpu addr (hex) r/w i 2 c addr (hex) default notes
data sheet MVTX2803Ag 25 semicmf.019 int_mask2 inte rrupt mask 2 308 r/w na ff int_mask3 inte rrupt mask 3 309 r/w na ff int_status0 status of masked interrupt register0 30a ro na int_status1 status of masked interrupt register1 30b ro na intp_mask?n? interrupt mask for mac port 2n, 2n+1 ( n=0-3) 30c-30f r/w na ff rqs receive queue select 310 r/w na 00 rqss receive queue status 311 ro na tx_age transmission queue aging time 312 r/w 03b 08 search engine configurations agetime_low mac ad dress aging time low 400 r/w 03c 2c agetime_high mac address aging time high 401 r/w 03d 00 v_agetime vlan to port aging time 402 r/w na ff se_opmode search engine operation mode 403 r/w na 00 scan scan control register 404 r/w na 00 buffer control and qos control fcbat fcb aging timer 500 r/w 03e ff qosc qos control 501 r/w 03f 00 fcr flooding control register 502 r/w 040 08 avpml vlan priority map low 503 r/w 041 88 avpmm vlan priority map middle 504 r/w 042 c6 avpmh vlan priority map high 505 r/w 043 fa tospml tos priority map low 506 r/w 044 88 tospmm tos priority map middle 507 r/w 045 c6 tospmh tos priority map high 508 r/w 046 fa avdm vlan discard map 509 r/w 047 00 tosdml tos discard map 50a r/w 048 00 bmrc broadcast/multicast rate control 50b r/w 049 00 ucc unicast congestion control 50c r/w 04a 07 mcc multicast congestion control 50d r/w 04b 48 register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2803Ag data sheet semicmf.019 26 pr100 port reservation for 10/100 ports 50e r/w 04c 00 prg port reservation for giga ports 50f r/w 04d 26 sfcb share fcb size 510 r/w 04e 37 c2rs class 2 reserved size 511 r/w 04f 00 c3rs class 3 reserved size 512 r/w 050 00 c4rs class 4 reserved size 513 r/w 051 00 c5rs class 5 reserved size 514 r/w 052 00 c6rs class 6 reserved size 515 r/w 053 00 c7rs class 7 reserved size 516 r/w 054 00 qosc?n? qos control (n=0 ? 2f) 517?546 r/w 055-084 qosc?n? qos control (n=30 ? 82) 547-599 r/w na rdrc0 wred rate control 0 59a r/w 085 8e rdrc1 wred rate control 1 59b r/w 086 68 misc configuration registers mii_op0 mii register option 0 600 r/w 0b1 00 mii_op1 mii register option 1 601 r/w 0b2 00 fen feature registers 602 r/w 0b3 10 miic0 mii command register 0 603 r/w n/a 00 miic1 mii command register 1 604 r/w n/a 00 miic2 mii command register 2 605 r/w n/a 00 miic3 mii command register 3 606 r/w n/a 00 miid0 mii data register 0 607 ro n/a 00 miid1 mii data register 1 608 ro n/a 00 led led control register 609 r/w 0b4 38 device device id and test 60a r/w 0b5 00 checksum eeprom checksum register 60b r/w 0c5 00 leduser0 led user define register 0 60c r/w 0bb 00 leduser1 led user define register 1 60d r/w 0bc 00 leduser2 led user define reg. 2/led_byte pin 2 60e r/w 0bd 80 leduser3 led user define reg. 3/led_byte pin 3 60f r/w 0be 33 register description cpu addr (hex) r/w i 2 c addr (hex) default notes
data sheet MVTX2803Ag 27 semicmf.019 leduser4 led user define reg. 4/led_byte pin 4 610 r/w 0bf 32 leduser5 led user define reg. 5/led_byte pin 5 611 r/w 0c0 20 leduser6 led user define reg. 6/led_byte pin 6 612 r/w 0c1 40 leduser7 led user define reg. 7/led_byte pin 1 & 0 613 r/w 0c2 61 miinp0 mii next page data register0 614 r/w 0c3 00 miinp1 mii next page data register1 615 r/w 0c4 00 test group control dtsrl test register low e00 r/w n/a 00 dtsrm test register medium e01 r/w n/a 01 dtsrh test register high e02 r/w n/a 00 tdrb0 test mux read back register [7:0] e03 ro n/a tdrb1 test mux read back register [15:8] e04 ro n/a dtcr test counter register e05 r/w n/a 00 mask0 mask timeout 0 e06 r/w 0b6 00 mask1 mask timeout 1 e07 r/w 0b7 00 mask2 mask timeout 2 e08 r/w 0b8 00 mask3 mask timeout 3 e09 r/w 0b9 00 mask4 mask timeout 4 e0a r/w 0ba 00 device configuration register gcr global control register f00 r/w n/a 00 dcr device status and signature register f01 ro n/a dcr01 gigabit port0 port1 status register f02 ro na dcr23 gigabit port2 port3 status register f03 ro na dcr45 gigabit port4 port5 status register f04 ro na dcr67 gigabit port6 port7 status register f05 ro na register description cpu addr (hex) r/w i 2 c addr (hex) default notes
MVTX2803Ag data sheet semicmf.019 28 note: 1. se = search engine note: 2. fe = frame engine note: 3. pgs = port group01, 23, 45, and 67 note: 4. mc = mac control note: 5. tm = time dpst device port status register f06 r/w n/a 00 dtst data read back register f07 ro n/a pllcr pll control register f08 r/w n/a 00 lclkcr lclk control register f09 r/w n/a 00 bclkcr bclk control register f0a r/w n/a 00 bstrrb0 boot strap read back register 0 f0b ro n/a bstrrb1 boot strap read back register 1 f0c ro n/a bstrrb2 boot strap read back register 2 f0d ro n/a bstrrb3 boot strap read back register 3 f0e ro n/a bstrrb4 boot strap read back register 4 f0f ro n/a bstrrb5 boot strap read back register 5 f10 ro n/a da da register fff ro n/a da register description cpu addr (hex) r/w i 2 c addr (hex) default notes
data sheet MVTX2803Ag 29 semicmf.019 10.2 group 0 address - mac ports group 10.2.1 ecr1pn: port n control register i 2 c address h00+2n; serial interface address:h000+2n (n=0 to 7) accessed by serial interface and i 2 c (r/w) 7 65 4321 0 sp state a-fc port mode bit [4:0] ? port mode (default 2?b00) bit [4:3] 00 - automatic enable auto-negotiation ? this enables hardware state machine for auto-negotiation. 01 - limited disable auto-negotiation ? this disables hardware for speed auto-negotiation. hardware polls mii for link status. 10 - link down - force link down (disabl e the port). does not talk to phy. 11 - link up ? does not talk to phy. user erc1 [2:0] for config. bit [2] 1 ? 10mbps (default 1?b0) 0 ? 100mbps bit 2 is used only when the port is in mii (10/100) mode. bit [1] 1 ? half duplex (do not use) (default 1?b0) 0 ? full duplex
MVTX2803Ag data sheet semicmf.019 30 bit [0] 1 ? flow control off (default 1?b0) 0 ? flow control on ? when flow control is on: ? in full duplex mode, the mac transmitt er sends flow control frames when necessary. the mac receiver interprets and processes incomming flow control frames. the flow control frame received counter is incremented whenever a flow control frame is received. ? when flow control is off: ? in full duplex mode, the mac transmi tter does not send flow control frames. the mac receiver does not interpret or process the flow control frames. the flow control frame receiver counter is not incremented. bit [5] ? asymmetric flow control enable. 0 ? disable asymmetric flow control 1 ? enable asymmetric flow control ? when this bit is set, and flow control is on (bit[0] = 0), don?t send out a flow control frame. but mac receiver interprets and process flow control frames. ( default is 0) bit [7:6] ? ss - spanning tree state (802.1d spanning tree protocol). (default 2?b11) 00 ? blocking: frame is dropped 01 - listening: frame is dropped 10 - learning: frame is dropped. source mac address is learned. 11 - forwarding: frame is forw arded. source mac address is learned.
data sheet MVTX2803Ag 31 semicmf.019 10.2.2 ecr2pn: port n control register i 2 c address: 01+2n; serial inte rface address:h001+2n (n=0to7) accessed by serial interface (r/w) 70 security en rtsel disl ftf futf bit[0]: ? filter untagged frame (default 0) 0: disable 1: enable ? all untagged frames from th is port are discarded or follow secu- rity option when security is enable bit[1]: ? filter tag frame (default 0) 0: disable 1: enable - all tagged frames from this port are discarded or follow security option when security is enable bit[2]: ? learning disable (default 0) 0: learning is enabled on this port 1: learning is disabled on this port bit[3]: ? reserved bit [5:4:] ? reserved bit[7:6] ? security enable (default 00). the mvtx2804ag checks the incoming data for one of the following conditions: ? if the source mac address of the incoming packet is in the mac table and is defined as secure address but the ingr ess port is not the same as the port associated with the mac address in the mac table. ? a mac address is defined as secure w hen its entry at mac table has static status and bit 0 is set to 1. mac address bit 0 (the first bit transmitted) indicates whether the address is unicast or multicast. as source addresses are always unicast bit 0 is not used (always 0). mvtx2804 uses this bit to define secure mac addresses. ? if the port is set as learning disable and the source mac address of the incoming packet is not defined in the mac address table. ? if the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. ? if one of these three conditions occurs, the packet will be handled according to one of the following specified options: 00 ? disable port security 01 ? enable port security. port will be disabled when security violation is detected 10 ? n/a 11 ? n/a
MVTX2803Ag data sheet semicmf.019 32 10.2.3 ecrmisc1 ? cpu port control register misc1 i 2 c address h10, serial interfce address:h010 access by serial interface and i 2 c (r/w) 10.2.4 ecrmisc2 ? cpu port control register misc2 (i 2 c address h11, serial interface address:011) access by serial interface and i 2 c (r/w) 10.2.5 ggcontrol 0? extra giga port control serial interface address:h012 accessed by and serial interface (r/w) 7 50 ss state reserved bit [7:0] ? reserved 7 0 security en rtsel disl ftf futf bit [7:0] ? reserved 754 10 dfc1 di1 mii1 rst1 dfc0 di0 mii0 rst0 bit[0]: ? reset giga port 0 ( default is 0) 0: normal operation 1: reset gigabit port 0. bit[1]: ? giga port 0 use mii interface (10/100m) ( default is 0) 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[2]: ? reserved -must be '0' (default 0) bit[3]: ? reserved ? must be ?0? bit[4]: ? reset giga port 1 ( default 0) 0: normal operation 1: reset gigabit port 1.
data sheet MVTX2803Ag 33 semicmf.019 10.2.6 ggcontrol 1? extra giga port control serial interface address:h013 accessed by cpu and serial interface (r/w) 10.2.7 ggcontrol 2? extra giga port control serial interface address:h014 accessed by cpu and serial interface (r/w) bit[5]: ? giga port 1 use mii interface (10/100m) ( default 0) 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[6]: ? reserved - must be '0' (default 0) bit[7]: ? reserved ? must be ?0? 754 10 dfc3 di3 mii3 rst3 dfc2 di2 mii2 rst2 bit[0]: ? reset giga port 2 default is 0 0: normal operation 1: reset gigabit port 2 bit[1]: ? giga port 2 use mii interface (10/100m) default is 0 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[2]: ? reserved - must be '0' (default '0') bit[3]: ? reserved ? must be ?0? bit[4]: ? reset giga port 3 default is 0 0: normal operation 1: reset gigabit port 3. bit[5]: ? giga port 3 use mii interface (10/100m) default is 0 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[6]: ? reserved - must be '0' (default '0') bit[7]: ? reserved ? must be ?0? 754 10 dfc5 di5 mii5 rst5 dfc4 di4 mii4 rst4
MVTX2803Ag data sheet semicmf.019 34 10.2.8 ggcontrol 3? extra giga port control serial interface address:h015 accessed by cpu and serial interface (r/w) bit[0]: ? reset giga port 4 default is 0 0: normal operation 1: reset gigabit port 4. bit[1]: ? giga port 4 use mii interface (10/100m) default is 0 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[2]: ? reserved - must be '0' (default 0) bit[3]: ? reserved ? must be ?0? bit[4]: ? reset giga port 5 default is 0 0: normal operation 1: reset gigabit port 5. bit[5]: ? giga port 5 use mii interface (10/100m) default is 0 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[6]: ? reserved - must be '0' (default 0) bit[7]: ? reserved ? must be ?0? 754 10 dfc7 di7 mii7 rst7 dfc6 di6 mii6 rst6 bit[0]: ? reset giga port 6 default is 0 0: normal operation 1: reset gigabit port 6. bit[1]: ? giga port 6 use mii interface (10/100m) default is 0 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[2]: ? reserved - must be '0' (default 0) bit[3]: ? reserved ? must be ?0? bit[4]: ? reset giga port 7 default is 0 0: normal operation 1: reset gigabit port 7.
data sheet MVTX2803Ag 35 semicmf.019 10.3 group 1 address - vlan group 10.3.1 avtcl ? vlan type code register low i 2 c address h12; serial interface address:h100 accessed by serial interface and i 2 c (r/w) 10.3.2 avtch ? vlan type code register high i 2 c address h13; serial interface address:h101 accessed by serial interface and i 2 c (r/w) bit [7:0] vlantype_high: upper 8 bits of the vlan type code (default is 81) 10.3.3 pvmap00_0 ? port 00 configuration register 0 i 2 c address h14, serial interface address:h102 accessed by serial interface and i 2 c (r/w) port based vlan mode this register indicates the legal egress ports. example: a ?1? on bit 7 means that packets arriving on port 0 can be sent to port 7. a ?0? on bit 7 means that any packet destined to port 7 will be discarded. 10.3.4 pvmap00_1 ? port 00 configuration register 1 i 2 c address h15, serial interface address:h103 accessed by serial interface and i 2 c (r/w) port based vlan mode bit[5]: ? giga port 7 use mii interface (10/100m) default is 0 0: gigabit port operation at 1000m mode 1: gigabit port operation at 10/100m mode (mii) bit[6]: ? reserved - must be '0' (default 0) bit[7]: ? reserved ? must be ?0? bit[7:0]: vlantype_low: lower 8 bits of the vlan type code (default 00) bit[7:0]: ? vlan mask for ports 7 to 0 (default ff) 0 ? disable 1 - enable bit[7:0]: reserved (default is ff)
MVTX2803Ag data sheet semicmf.019 36 10.3.5 pvmap00_2 ? port 00 configuration register 2 i 2 c address h16, serial interface address:h104 accessed by serial interface and i 2 c (r/w) this registered is unused 10.3.6 pvmap00_3 ? port 00 configuration register 3 i 2 c address h17, serial interface address:h105) accessed by serial interface and i 2 c (r/w) port based mode 765 3210 fp en drop default tx priority fnt if reserved bit [1:0]: ? reserved (default 0) bit [2]: ? force untagout (default 0) 0 disable 1 force untag output all packets transmitted from this port are untagged. this register is used when this port is connected to le gacy equipment that does not support vlan tagging. bit [5:3]: ? fixed transmit priority. used when bit[7] = 1 (default 0) 000 transmit priority level 0 (lowest) 001 transmit priority level 1 010 transmit priority level 2 011 transmit priority level 3 100 transmit priority level 4 101 transmit priority level 5 110 transmit priority level 6 111 transmit priority level 7 (highest) bit [6]: ? fixed discard priority (default 0) 0 ? discard priority level 0 (lowest) 1 ? discard priority level 7(highest) bit [7]: ? enable fix priority (default 0) 0 disable fix priority. all frames are analyzed. transmit priority and drop priority are based on vlan tag, tos or logical port. 1 transmit priority and discard priority are based on values programmed in bit [6:3]
data sheet MVTX2803Ag 37 semicmf.019 port vlan map pvmap00_0,1,2,3 i 2 c address h14,15,16,17; serial interface address:h102,103,104,105) pvmap01_0,1,2,3 i 2 c address h18,19,1a,1b; serial interface address:h106,107,108,109) pvmap02_0,1,2,3 i 2 c address h1c,1d,1e,1f; serial in terface address:h10a, 10b, 10c, 10d) pvmap03_0,1,2,3 i 2 c address h20,21,22,23; serial interface address:h10e, 10f, 110, 111) pvmap04_0,1,2,3 i 2 c address h24,25,26,27; serial interface address:h112, 113, 114, 115) pvmap05_0,1,2,3 i 2 c address h28,29,2a,2b; serial interface address:h116, 117, 118, 119) pvmap06_0,1,2,3 i 2 c address h2c,2d,2e,2f; serial interface address:h11a, 11b, 11c, 11d) pvmap07_0,1,2,3 i 2 c address h30,31,32,33; serial interface address:h11e, 11f, 120, 121) pvmap08_0,1,2,3 i 2 c address h34,35,36,37; serial interface address:h122, 123, 124, 125) (reserved) 10.3.7 pvmode i 2 c address: h038, serial interface address:h126 accessed by serial interface (r/w) 10.4 group 2 address - port trunking group 10.4.1 trunk0 ? trunk group 0 me mber (managed mode only) serial interface address:h200 accessed by serial interface (r/w) bit [7:0] reserved 74310 ro mp bpdu dm reserved vmod bit [0]: ? reserved must be '0' bit [4]: ? disable mac address 0 0: mac address 0 is not leaned. 1: mac address 0 is leaned. bit [5]: ? force bpdu as multicast frame ( default 0 ) 1: enable. bpdu frames (frames with destination mac address in the range of 01-80-c2 00-00-00 through 01-80-c2-00-00-0f) are forwarded as multicast frames. 0: disable. drop frames in this range. bit [6]: ? mac/port 0: single mac address per system 1: single mac address per port bit [7]: ? reserved
MVTX2803Ag data sheet semicmf.019 38 10.4.2 trunk1 ? trunk group 1 member (managed mode only) serial interface address:h201 accessed by serial interface (r/w) bit [7:0] reserved 10.4.3 trunk2? trunk group 2 member (managed mode only) serial interface address:h202 accessed by serial interface (r/w) bit [7:0] reserved 10.4.4 trunk3? trunk group 3 member (managed mode only) serial interface address:203 accessed by serial interface and i 2 c (r/w) bit [7:0] reserved 10.4.5 trunk_hash_mode ? trunk hash mode serial interface address:h206 accessed by serial interface (r/w) bit [7:0] reserved 10.4.6 trunk0_mode ? tru nk group 0 and 1 mode i 2 c address: h039, serial interface address:h207 accessed by serial interface and i 2 c (r/w) port selection in unmanaged mode. trunk group 0 and trunk group 1 are enable accordingly to bit [1:0] when input pin p_d[9] = 0 (external pull down). 10.4.7 trunk0_hash0 ? trunk group 0 hash result 0,1,2 destination port number serial interface address:h208 reserved 70 port sel bit [1:0]: ? port member selection for trunk 0 and 1 in unmanaged mode (default 2?b00) 00 ? only trunk group 0 is enable. port 0 and 1 are used for trunk group0 01 ? only trunk group 0 is enable. port 0,1 and 2 are used for trunk group0 10 ? only trunk group 0 is enable. port 0,1,2 and 3 are used for trunk group0 11 ? trunk group 0 and 1 are enable. port 0, 1 used for trunk group0, and port 2 and 3 are used for trunk group1
data sheet MVTX2803Ag 39 semicmf.019 10.4.8 trunk0_hash1 ? trunk group 0 hash r esult 2,3,4,5 destination port number serial interface address:h209 reserved 10.4.9 trunk0_hash2 ? trunk group 0 hash r esult 5,6,7 destinat ion port number serial interface address:h20a reserved 10.4.10 trunk0_hash3 ? trunk group 0 hash r esult 8,9,10 destina tion port number serial interface address:h20b reserved 10.4.11 trunk0_hash4 ? trunk group 0 hash resu lt 10,11,12,13 desti nation port number serial interface address:h20c reserved 10.4.12 trunk0_hash5 ? trunk group 0 hash resu lt 13,14,15 destination port number serial interface address:h20d reserved 10.4.13 trunk1_mode ? trunk gr oup 1 mode (unmanaged mode) i 2 c address h03a; serial interface address:h20e accessed by serial interface and i 2 c (r/w) port selection in unmanaged mode. trunk group 2 and trunk group 3 are enable accordingly to bits [1:0] when input pin p_d[10] = 0 (external pull down). 10.4.14 trunk1_hash0 ? trunk group 1 hash r esult 0, 1, 2 dest ination port number serial interface address:h20f reserved 73210 port select bit [1:0]: ? port member selection for trunk 2 and 3 in unmanaged mode 00 ? only trunk group 2 is enable. port 4 and 5 are used for trunk group2 01 ? only trunk group 2 is enable. port 4, 5 and 6 are used for trunk group2 10 ? only trunk group 2 is enable. port 4, 5, 6 and 7 are used for trunk group2 11 ? trunk group 2 and trunk group 3 are enable. port 4 and used for trunk group2, and port 6 5 are and 7 are used for trunk group3
MVTX2803Ag data sheet semicmf.019 40 10.4.15 trunk1_hash1 ? trunk gro up 1 hash result 2, 3, 4, 5 destination port number serial interface address:h210 reserved 10.4.16 trunk1_hash2 ? trunk group 1 hash re sult 5, 6, 7 desti nation port number serial interface address:h211 reserved 10.4.17 trunk1_hash3 ? trunk gro up 1 hash result 8, 9, 10 destination port number serial interface address:h212 reserved 10.4.18 trunk1_hash4? trunk grou p 1 hash result 11, 12, 13 destination port number serial interface address:h213 reserved 10.4.19 trunk1_hash5 ? trunk group 1 hash re sult 13, 14, 15 dest ination port number serial interface address:h214 reserved 10.4.20 trunk2_hash0 ? trunk group 2 hash re sult 0, 1, 2 desti nation port number serial interface address:h215 reserved 10.4.21 trunk2_hash1 ? trunk gro up 2 hash result 2, 3, 4, 5 destination port number serial interface address:h216 reserved 10.4.22 trunk2_hash2 ? trunk group 2 hash re sult 5, 6, 7 desti nation port number serial interface address:h217 reserved 10.4.23 trunk2_hash3 ? trunk gro up 2 hash result 8, 9, 10 destination port number serial interface address:h218 reserved 10.4.24 trunk2_hash4 ? trunk gro up 2 hash result 10, 11, 12, 13 destination port number serial interface address:h219 reserved 10.4.25 trunk2_hash5 ? trunk group 2 hash re sult 13, 14, 15 dest ination port number serial interface address:h21a reserved
data sheet MVTX2803Ag 41 semicmf.019 10.4.26 trunk3_hash0 ? trunk group 3 hash r esult 0, 1, 2 dest ination port number serial interface address:h21b reserved 10.4.27 trunk3_hash1 ? trunk group 3 hash resu lt 2, 3, 4, 5 dest ination port number serial interface address:h21c reserved 10.4.28 trunk3_hash2 ? trunk group 3 hash r esult 5, 6, 7 dest ination port number serial interface address:h21d reserved 10.4.29 trunk3_hash3 ? trunk group 3 hash resu lt 8, 9, 10 dest ination port number serial interface address:h21e reserved 10.4.30 trunk3_hash4 ? trunk gro up 3 hash result 10, 11, 12, 13 destination port number serial interface address:h21f reserved 10.4.31 trunk3_hash5 ? trunk group 3 hash resu lt 13, 14, 15 destin ation port number serial interface address:h220 reserved 10.4.32 multicast hash registers 10.4.33 multicast_hash00 ? multicast hash result0 mask byte [7:0] serial interface address:h221 accessed by serial interface (r/w) reserved 10.4.34 multicast_hash01 ? multicast hash result1 mask byte [7:0] serial interface address:h222 accessed by serial interface (r/w) reserved 10.4.35 multicast_hash02 ? multicast hash result2 mask byte [7:0] serial interface address:h223 accessed by serial interface (r/w) reserved
MVTX2803Ag data sheet semicmf.019 42 10.4.36 multicast_hash03 ? multicast hash result3 mask byte [7:0] serial interface address:h224 accessed by serial interface (r/w) reserved 10.4.37 multicast_hash04 ? multicast hash result4 mask byte [7:0] serial interface address:h225 accessed by serial interface (r/w) reserved 10.4.38 multicast_hash05 ? multicast hash result5 mask byte [7:0] serial interface address:h226 accessed by serial interface (r/w) reserved 10.4.39 multicast_hash06 ? multicast hash result6 mask byte [7:0] serial interface address:h227 accessed by serial interface (r/w) reserved 10.4.40 multicast_hash07 ? multicast hash result7 mask byte [7:0] serial interface address:h228 accessed by serial interface (r/w) reserved 10.4.41 multicast_hash08 ? multicast hash result8 mask byte [7:0] serial interface address:h229 accessed by serial interface (r/w) reserved 10.4.42 multicast_hash09 ? multicast hash result9 mask byte [7:0] serial interface address:h22a accessed by serial interface (r/w) reserved 10.4.43 multicast_hash10 ? multicast hash result10 mask byte [7:0] serial interface address:h22b accessed by serial interface (r/w) reserved
data sheet MVTX2803Ag 43 semicmf.019 10.4.44 multicast_hash11 ? multicast hash result11 mask byte [7:0] serial interface address:h22c accessed by serial interface (r/w) reserved 10.4.45 multicast_hash12 ? multicast hash result12 mask byte [7:0] serial interface address:h22d accessed by serial interface (r/w) reserved 10.4.46 multicast_hash13 ? multicast hash result13 mask byte [7:0] serial interface address:h22e accessed by serial interface (r/w) reserved 10.4.47 multicast_hash14 ? multicast hash result14 mask byte [7:0] serial interface address:h22f accessed by serial interface (r/w) reserved 10.4.48 multicast_hash15 ? multicast hash result15 mask byte [7:0] serial interface address:h230 accessed by serial interface (r/w) reserved 10.4.49 multicast_hashml ? multicast hash bit[8] for result7-0 serial interface address:h231 accessed by serial interface (r/w) reserved 10.4.50 multicast_hashmh ? multicast hash bit[8] for result 15-8 serial interface address:h232 accessed by serial interface (r/w) reserved 10.5 group 3 address - cpu port configuration group 10.5.1 mac0 ? cpu mac address byte 0 serial interface address:h300 reserved
MVTX2803Ag data sheet semicmf.019 44 10.5.2 mac1 ? cpu mac address byte 1 serial interface address:h301 reserved 10.5.3 mac2 ? cpu mac address byte 2 serial interface address:h302 reserved 10.5.4 mac3 ? cpu mac address byte 3 serial interface address:h303 reserved 10.5.5 mac4 ? cpu mac address byte 4 serial interface address:h304 reserved 10.5.6 mac5 ? cpu mac address byte 5 serial interface address:h30 reserved 10.5.7 int_mask0 ? interrupt mask 0 serial interface address:h306 reserved 10.5.8 int_mask1 ? interrupt mask 1 serial interface address:h307 reserved 10.5.9 int_status0 ? masked interrupt status register0 serial interface address:h30a reserved 10.5.10 int_status1 ? masked interrupt status register1 serial interface address:h30b reserved 10.5.11 intp_mask0 ? interrupt mask for mac port 0,1 serial interface address:h30c reserved 10.5.12 intp_mask1 ? interrupt mask for mac port 2,3 serial interface address:h30d reserved
data sheet MVTX2803Ag 45 semicmf.019 10.5.13 intp_mask4 ? interrupt mask for mac port 4,5 serial interface address:h30e reserved 10.5.14 intp_mask5 ? interrupt mask for mac port 6,7 serial interface address:h30f reserved 10.5.15 rqs ? receive queue select serial interface address:h310 reserved 10.5.16 rqss ? receive queue status serial interface address:h311 reserved 10.5.17 tx_age ? tx queue aging timer i 2 c address: h03b;serial interface address:h312 accessed by serial interface and i 2 c (r/w) bit[4:0]: unit of 100ms (default 8). disabl e transmission queue aging if value is zero. bit[5]must be set to ?0? bit[7:6]: reserved 10.6 group 4 address - search engine group 10.6.1 agetime_low ? mac address aging time low i 2 c address: h03c; serial interface address:h400 accessed by serial interface and i 2 c (r/w) bit [7:0] low byte of the mac address aging timer. (default 2c) mac address aging is enable/dis able by boot strap t_d[9]. 10.6.2 agetime_high ?mac address aging time high i 2 c address h03d; serial interface address h401 accessed by serial interface and i 2 c (r/w) bit [7:0]: high byte of the ma c address aging timer. (default 00) aging time is based on the following equation: {agetime_time,agetime_low} x (# of mac entries x100sec) 75 0 tx queue agent
MVTX2803Ag data sheet semicmf.019 46 note: the numer of entries= 66k when t_d[5] is pull down (sram memory size = 512k) and 34k when t_d[5] is pull up (sram memory size = 256k). 10.6.3 v_agetime ? vlan to port aging time serial interface address h402 reserved 10.6.4 se_opmode ? search engine operation mode serial interface address:h403 accessed by cpu (r/w) 10.6.5 scan ? scan control register serial interface address: h404 reserved 10.7 group 5 address - buffer control/qos group 10.7.1 fcbat ? fcb aging timer i 2 c address: h03e; serial interface address:h500 7 6 543 2 1 0 sl dms da bit [0]: ? reserved bit [1]: ? reserved bit [2]: ? reserved bit [3]: ? reserved bit [4]: ? reserved bit [5]: ? reserved bit [6]: ? disable mct speedup aging (default 0) 1 ? disable speedup aging when mct resource is low. 0 ? enable speedup aging when mct resource is low. bit [7]: ? slow learning (default 0) 1? enable slow learning. learning is temporary disabled when search demand is high 0 ? learning is performed independent of search demand 70 fcbat
data sheet MVTX2803Ag 47 semicmf.019 10.7.2 qosc ? qos control i 2 c address: h03f; serial interface address:h501 accessed by serial interface and i 2 c (r/w) 10.7.3 fcr ? flooding control register i 2 c address: h040; serial interface address:h502 accessed by serial interface and i 2 c (r/w) bit [7:0]: ? fcb aging time. unit of 1ms. ( default ff ) ? fcbat define the aging time out interval of fcb handle 70 tos-d tos-p vf1c fb bit [0]: ? qos frame lost is ok. priority will be available for flow control enabled source only when this bit is set (default 0) bit [4]: ? per vlan (port based) multicast flow control (default 0) 0 ? disable 1 - enable bit [5]: ? reserved bit [6]: ? select tos bits for priority (default 0) 0 ? use tos [4:2] bits to map the transmit priority 1 ? use tos [5:3] bits to map the transmit priority bit [7]: ? select tos bits for drop (default 0) 0 ? use tos [4:2] bits to map the drop priority 1 ? use tos [5:3] bits to map the drop priority 70 tos timebase u2mr bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of time base defined in bits [6:4]. this is used to limit the amount of flooding traffic. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to disable this function, program u2mr to 0. ( default = 4?h8 )
MVTX2803Ag data sheet semicmf.019 48 10.7.4 avpml ? vlan priority map i 2 c address: h041; serial interface address:h503 accessed by serial interface and i 2 c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan priorities to map into eight internal level transmit priorities. under the internal transmit priority, seven? is the highest priority where as zero? is the lowest. this feature allows the user the flexibility of redefining the vlan priority field. for example, programming a value of 7 into bit 2:0 of the avpml register would map packet vl an priority ) into internal transmit priority 7. the new priority is used only inside the 2804. when the pack et goes out it carries the original priority. 10.7.5 avpmm ? vlan priority map i 2 c address: h042, serial interface address:h504 accessed by serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: bit [6:4]: ? timebase : (default = 000) 000 = 10us 001 = 20us 010 = 40us 011 = 80us 100 = 160us 101 = 320us 110 = 640us 111 = 10us, same as 000. bit [7]: ? select vlan tag or tos field (ip packets) to be preferentially picked to map transmit priority and drop priority ( default = 0 ). 0 ? select vlan tag priority field over tos field 1 ? select tos field over vlan tag priority field 70 bit [2:0]: mapped priority of 0 (default 000) bit [5:3]: mapped priority of 1 (default 001) bit [7:6]: mapped priority of 2 (default 10) 70 bit [0]: mapped priority of 2 (default 0) bit [3:1]: mapped priority of 3 (default 011)
data sheet MVTX2803Ag 49 semicmf.019 10.7.6 avpmh ? vlan priority map i 2 c address: h043, serial interface address:h505 accessed by serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 10.7.7 ospml ? tos priority map i 2 c address: h044, serial interface address:h506 accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities 10.7.8 tospmm ? tos priority map i 2 c address: h045, serial interface address:h507 accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities bit [6:4]: mapped priority of 4 (default 100) bit [7]: mapped priority of 5 (default 1) 70 bit [1:0]: mapped priority of 5 (default 10) bit [4:2]: mapped priority of 6 (default 110) bit [7:5]: mapped priority of 7 (default 111) 70 bit [2:0]: mapped priority when tos is 0 (default 000) bit [5:3]: mapped priority when tos is 1 (default 001) bit [7:6]: mapped priority when tos is 2 (default 10) 70 bit [0]: mapped priority when tos is 2 (default 0) bit [3:1]: mapped priority when tos is 3 (default 011)
MVTX2803Ag data sheet semicmf.019 50 10.7.9 tospmh ? tos priority map i 2 c address: h046, serial interface address:h508 accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities: 10.7.10 avdm ? vlan discard map i 2 c address: h047, serial interface address:h509 accessed by serial interface and i 2 c (r/w) map vlan priority into frame discard when low priori ty buffer usage is above threshold. frames with high discard (drop) priority will be discarded (dropped) before frames with low drop priority. ? 0 ? low discard priority ? 1 ? high discard priority 10.7.11 tosdml ? tos discard map i 2 c address: h048, serial interface address:h50a bit [6:4]: mapped priority when tos is 4 (default 100) bit [7]: mapped priority when tos is 5 (default 1) 70 bit [1:0]: mapped priority when tos is 5 (default 01) bit [4:2]: mapped priority when tos is 6 (default 110) bit [7:5]: mapped priority when tos is 7 (default 111) 70 bit [0]: frame discard priority for fram es with vlan transmit priority 0 (default 0) bit [1]: frame discard priority for fram es with vlan transmit priority 1 (default 0) bit [2]: frame discard priority for fram es with vlan transmit priority 2 (default 0) bit [3]: frame discard priority for fram es with vlan transmit priority 3 (default 0) bit [4]: frame discard priority for fram es with vlan transmit priority 4 (default 0) bit [5]: frame discard priority for fram es with vlan transmit priority 5 (default 0) bit [6]: frame discard priority for fram es with vlan transmit priority 6 (default 0) bit [7]: frame discard priority for fram es with vlan transmit priority 7 (default 0)
data sheet MVTX2803Ag 51 semicmf.019 accessed by serial interface and i 2 c (r/w) map tos into frame discard when low priority buffer usage is above threshold 10.7.12 bmrc - broadcast/multicast rate control i 2 c address: h049, serial interface address:h50b accessed by serial interface and i 2 c (r/w) this broadcast and multicast rate defines for each port the number of incoming packet allowed to be forwarded within a specified time. once the packet rate is reac hed, packets will be dropped. to turn off the rate limit, program the field to 0. 70 bit [0]: frame discard priority for frames with tos transmit priority 0 (default 0) bit [1]: frame discard priority for frames with tos transmit priority 1 (default 0) bit [2]: frame discard priority for frames with tos transmit priority 2 (default 0) bit [3]: frame discard priority for frames with tos transmit priority 3 (default 0) bit [4]: frame discard priority for frames with tos transmit priority 4 (default 0) bit [5]: frame discard priority for frames with tos transmit priority 5 (default 0) bit [6]: frame discard priority for frames with tos transmit priority 6 (default 0) bit [7]: frame discard priority for frames with tos transmit priority 7 (default 0) 70 broadcast rate multicast rate bit [3:0] : multicast rate co ntrol number of multicast pa ckets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) . bit [7:4] : broadcast rate co ntrol number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0)
MVTX2803Ag data sheet semicmf.019 52 10.7.13 ucc ? unicast congestion control i 2 c address: h04a, serial interface address: h50c accessed by serial interface and i 2 c (r/w) 10.7.14 mcc ? multicast congestion control i 2 c address: h0b7, serial interface address: h50d accessed by serial interface and i 2 c (r/w) 10.7.15 prg ? port reservation for giga ports i 2 c address: h0b9, serial interface address h50f accessed by serial interface and i 2 c (r/w) 70 unicast congest threshold bit [7:0] : number of frame count. used for best effort dropping at b% when destination port?s best effort queue reaches ucc threshold and shared pool is all in use. granularity 16 frame. (default: h07) 70 fc reaction prd multicast congest threshold bit [3:0]: in multiples of two. used for tr iggering mc flow control when destination port?s best effort queue reaches mcc threshold. (default 5?h08) bit [4]: must be 0 bit [7:5]: flow control reaction period. ([7:5] *4)+3 usec (default 3?h2). 74 30 buffer low thd per source buffer reservation bit [3:0]: per source buffer reservation. defi ne the space in the fdb reserved for each port. expressed in multiples of 16 packets. for each packet 1536 bytes are reserved in the memory. default: 4?ha for 4mb memory 4?h6 for 2mb memory 4?h3 for 1mb memory
data sheet MVTX2803Ag 53 semicmf.019 fcb reservation 10.7.16 sfcb ? share fcb size i 2 c address: h04e, serial interface address h510 accessed by serial interface and i 2 c (r/w) 10.7.17 c2rs ? class 2 reserved size i 2 c address: h04f, serial interface address h511 accessed by serial interface and i 2 c (r/w) 10.7.18 c3rs ? class 3 reserved size i 2 c address: h050, serial interface address h512 accessed by serial interface and i 2 c (r/w) bits [7:4]: expressed in multip les of 16 packets. threshold for dropping all best effort frames when destination port best ef fort queues reach ucc threshold and shared pool is all used and source port reservation is at or below the prg[7:4] level. also the threshol d for initiating uc flow control. default: 4?h6 for 4mb memory 4?h2 for 2mb memory 4?h1 for 1mb memory 70 shared buffer size bits [7:0]: ? expressed in multiples of 8. buffer reservation for shared pool. (default 4g & 4m = 8?d62) (default 4g & 2m = 8?d20) (default 4g & 1m = 8'd08) (default 8g & 4m = 8?d150) (default 8g & 2m = 8?d55) (default 8g & 1m = 8'd25) 70 class 2 fcb reservation bits [7:0]: ? buffer reservation for class 2 (thi rd lowest priority). granularity 2. (default 8?h00) 70 class 3 fcb reservation
MVTX2803Ag data sheet semicmf.019 54 10.7.19 c4rs ? class 4 reserved size i 2 c address: h051, serial interface address h513 accessed by serial interface and i 2 c (r/w) 10.7.20 c5rs ? class 5 reserved size i 2 c address: h052; serial interface address: h514 accessed by serial interface and i 2 c (r/w) 10.7.21 c6rs ? class 6 reserved size i 2 c address: h053; serial interface address: h515 accessed by serial interface and i 2 c (r/w) 10.7.22 c7rs ? class 7 reserved size i 2 c address: h054; serial interface address: h516 accessed by serial interface and i 2 c (r/w) bits [7:0]: ? buffer reservation for class 3. granularity 2. (default 8?h00) 70 class 4 fcb reservation bits [7:0]: ? buffer reservation for class 4. granularity 2. (default 8?h00) 70 class 5 fcb reservation bits [7:0]: ? buffer reservation for class 5. granularity 2. (default 8?h00) 70 class 6 fcb reservation bits [7:0]: ? buffer reservation for class 6 (second highest priority). granularity 2. (default 8?h00) 70 class 7 fcb reservation
data sheet MVTX2803Ag 55 semicmf.019 classes byte gigabit port 0 10.7.23 qosc00 ? byte_c2_g0 i 2 c address: h055, serial interface address: h517 10.7.24 qosc01 ? byte_c3_g0 i 2 c address: h056, serial interface address: h518 10.7.25 qosc02 ? byte_c4_g0 i 2 c address: h057, serial interface address: h519 10.7.26 qosc03 ? byte_c5_g0 i 2 c address: h058, serial interface address: h51a 10.7.27 qosc04 ? byte_c6_g0 i 2 c address: h059, serial interface address: h51b bits [7:0]: ? buffer reservation for class 7 (hi ghest priority). granularity 2. (default 8?h00) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) 512byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64byte/unit when delay bound is used) (1024byte/unit when wfq is used)
MVTX2803Ag data sheet semicmf.019 56 10.7.28 qosc05 ? byte_c7_g0 i 2 c address: h05a, serial interface address: h51c qosc00 through qosc05 represent the values f-a in table 3 for gigabit port 0. they are per-queue byte thresholds for weighted random early drop (wred). qosc05 represents a, and qosc00 represents f. classes byte gigabit port 1 10.7.29 qosc06 ? byte_c2_g1 i 2 c address: h05b, serial interface address: h51d 10.7.30 qosc07 ? byte_c3_g1 i 2 c address: h05c, serial interface address: h51e 10.7.31 qosc08 ? byte_c4_g1 i 2 c address: h05d, serial interface address: h51f 10.7.32 qosc09 ? byte_c5_g1 i 2 c address: h05e, serial interface address: h520 bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0] byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
data sheet MVTX2803Ag 57 semicmf.019 10.7.33 qosc0a ? byte_c6_g1 i 2 c address: h05f, serial interface address: h521 10.7.34 qosc0b ? byte_c7_g1 i 2 c address: h060, serial interface address: h522 qosc06 through qosc0b represent the values f-a in t able 3. they are per-queue byte thresholds for random early drop. qosc0b represents a, and qosc06 represents f. classes byte gigabit port 2 10.7.35 qosc0c ? byte_c2_g2 i 2 c address: h061, serial interface address: h523 10.7.36 qosc0d ? byte_c3_g2 i 2 c address: h062, serial interface address: h524 10.7.37 qosc0e ? byte_c4_g2 i 2 c address: h063, serial interface address: h525 bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c7 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2803Ag data sheet semicmf.019 58 10.7.38 osc0f ? byte_c5_g2 i 2 c address: h064, serial interface address: h526 10.7.39 qosc10 ? byte_c6_g2 i 2 c address: h065, serial interface address: h27 10.7.40 qosc11 ? byte_c7_g2 i 2 c address: h066, serial interface address: h528 qosc0c through qosc11 represent the values f-a in table 3 for gigabit port 2. they are per-queue byte thresholds for random early drop. qosc11 represents a, and qosc0c represents f. classes byte gigabit port 3 10.7.41 qosc12 ? byte_c2_g3 i 2 c address: h067, serial interface address: h529 bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c7 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
data sheet MVTX2803Ag 59 semicmf.019 10.7.42 qosc13 ? byte_c3_g3 i 2 c address: h068, serial interface address: h52a 10.7.43 qosc14 ? byte_c4_g3 i 2 c address: h069, serial interface address: h52b 10.7.44 qosc15 ? byte_c5_g3 i 2 c address: h06a, serial interface address: h52c 10.7.45 qosc16 ? byte_c6_g3 i 2 c address: h06b, serial interface address: h52d 10.7.46 qosc17 ? byte_c7_g3 i 2 c address: h06c, serial interface address: h52e qosc12 through qosc17 represent the values f-a in table 3 for gigabit port 3. they are per-queue byte thresholds for random early drop. qosc1 7 represents a, and qosc12 represents f. bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c7 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2803Ag data sheet semicmf.019 60 classes byte gigabit port 4 10.7.47 qosc18 ? byte_c2_g4 i 2 c address: h06d, serial interface address:h 52f 10.7.48 qosc019 ? byte_c3_g4 i 2 c address: h06e, serial interface address: h530 10.7.49 qosc1a ? byte_c4_g4 i 2 c address: h06f, serial interface address: h531 10.7.50 qosc1b ? byte_c5_g4 i 2 c address: h070, serial interface address: h532 10.7.51 qosc1c ? byte_c6_g4 i 2 c address: h071, serial interface address: h533 bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c6 queue wred (default 8?h28) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
data sheet MVTX2803Ag 61 semicmf.019 10.7.52 qosc1d? byte_c7_g4 i 2 c address: h072, serial interface address: h534 qosc18 through qosc1d represent the values f-a in t able 3 for gigabit port 4. they are per-queue byte thresholds for random early drop. qosc1d represents a, and qosc18 represents f. classes byte gigabit port 5 10.7.53 qosc1e? byte_c2_g5 i 2 c address: h073, serial interface address: h535 10.7.54 qosc1f ? byte_c3_g5 i 2 c address: h074, serial interface address: h536 10.7.55 qosc20 ? byte_c4_g5 i 2 c address: h075, serial interface address: h537 10.7.56 qosc21 ? byte_c5_g5 i 2 c address: h076, serial interface address: h538 bits [7:0]: byte count threshold for c7 queue wred (default 8?h28) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2803Ag data sheet semicmf.019 62 10.7.57 qosc22 ? byte_c6_g5 i 2 c address: h077, serial interface address: h539 10.7.58 qosc23 ? byte_c7_g5 i 2 c address: h078, serial interface address: h53a qosc1e through qosc23 represent the values f-a in table 3 for gigabit port 5. they are per-queue byte thresholds for random early drop. qosc23 represents a, and qosc1e represents f. classes byte gigabit port 6 10.7.59 qosc24 ? byte_c2_g6 i 2 c address: h079, serial interface address: h53b 10.7.60 qosc25 ? byte_c3_g6 i 2 c address: h07a, serial interface address: h53c bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
data sheet MVTX2803Ag 63 semicmf.019 10.7.61 qosc26 ? byte_c4_g6 i 2 c address: h07b, serial interface address: h53d 10.7.62 qosc27 ? byte_c5_g6 i 2 c address: h07c, serial interface address: h53e 10.7.63 qosc28 ? byte_c6_g6 i 2 c address: h07d, serial interface address: h53f 10.7.64 qosc29 ? byte_c7_g6 i 2 c address: h07e, serial interface address:h 540 qosc24 through qosc29 represent the values f-a in table 3 for gigabit port 6. they are per-queue byte thresholds for random early drop. qosc2 9 represents a, and qosc24 represents f. classes byte gigabit port 7 10.7.65 qosc2a ? byte_c2_g7 i 2 c address: h07f, serial interface address: h541 bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c7 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c2 queue wred (default 8?h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2803Ag data sheet semicmf.019 64 10.7.66 qosc2b ? byte_c3_g7 i 2 c address: h080, serial interface address: h542 10.7.67 qosc2c ? byte_c4_g7 i 2 c address: h081, serial interface address: h543 10.7.68 qosc2d ? byte_c5_g7 i 2 c address: h082, serial interface address: h544 10.7.69 qosc2e ? byte_c6_g7 i 2 c address: h083, serial interface address: h545 10.7.70 qosc2f ? byte_c7_g7 i 2 c address: h084, serial interface address: h546 qosc00 through qosc05 represent the values f-a in table 3 for gigabit port 7. they are per-queue byte thresholds for random early drop. qosc05 represents a, and qosc00 represents f. bits [7:0]: byte count threshold for c3 queue wred (default 8?h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c4 queue wred (default 8?h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c6 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: byte count threshold for c5 queue wred (default 8?h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
data sheet MVTX2803Ag 65 semicmf.019 classes byte limit cpu 10.7.71 qosc30 ? byte_c01 serial interface address: h547 10.7.72 qosc31 ? byte_c02 serial interface address: h548 10.7.73 qosc32 ? byte_c03 serial interface address: h549 classes wfq credit set 0 10.7.74 qosc33 ? credit_c0_g0 serial interface address: h54a bits [7:0]: reserved bits [7:0]: reserved bits [7:0]: reserved bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 0 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4
MVTX2803Ag data sheet semicmf.019 66 see table below 10.7.75 qosc34 ? credit_c1_g0 serial interface address: h54b 10.7.76 qosc35 ? credit_c2_g0 serial interface address: h54c queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) 0= do not send any frames if the xoff is on. 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4?h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved
data sheet MVTX2803Ag 67 semicmf.019 10.7.77 qosc36 ? credit_c3_g0 serial interface address: h54d 10.7.78 qosc37 ? credit_c4_g0 serial interface address: h54e 10.7.79 qosc38 ? credit_c5_g0 serial interface address: h54f 10.7.80 qosc39? credit_c6_g0 serial interface address: h550 10.7.81 qosc3a? credit_c7_g0 serial interface address: h551 qosc33 through qosc3arepresents the set of wfq parame ters (see section 7.5) for gigabit port 0. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc33 corresponds to w0, and qosc3a corresponds to w7. in the 2g trunk configur ation, the sum of all values qosc33 through qosc3a must be equal to 128. classes wfq credit port g1 10.7.82 qosc3b ? credit_c0_g1 serial interface address: h552 bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved bits [5:0]: w0 - credit register for wfq. (default 6?h04)
MVTX2803Ag data sheet semicmf.019 68 see table below: 10.7.83 qosc3c ? credit_c1_g1 serial interface address: h54b bits [7:6]: ? priority type. define one of the four qos mode of operation for port 1 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4 queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) 0= do not send any frames if the xoff is on. 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4?h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
data sheet MVTX2803Ag 69 semicmf.019 10.7.84 qosc3d ? credit_c2_g1 serial interface address: h553 10.7.85 qosc3e ? credit_c3_g1 serial interface address: h554 10.7.86 qosc3f ? credit_c4_g1 serial interface address: h555 10.7.87 qosc40 ? credit_c5_g1 serial interface address: h556 10.7.88 qosc41? credit_c6_g1 serial interface address: h557 10.7.89 qosc42? credit_c7_g1 serial interface address: h558 qosc3b through qosc42 represents the set of wfq parameters (see section 7.5) for gigabit port 1. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc3b corresponds to w0, and qosc42 corresponds to w7. bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved
MVTX2803Ag data sheet semicmf.019 70 classes wfq credit port g2 10.7.90 qosc43 ? credit_c0_g2 serial interface address: h55a see table below: 10.7.91 qosc44 ? credit_c1_g2 serial interface address: h55b bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 2 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4 queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: flow control be queue only. (default 1?b1) 0= do not send any frames if the xoff is on. 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] w1 - credit register. (default 4?h04)
data sheet MVTX2803Ag 71 semicmf.019 10.7.92 qosc45 ? credit_c2_g2 serial interface address: h55c 10.7.93 qosc46 ? credit_c3_g2 serial interface address: h55d 10.7.94 qosc47 ? credit_c4_g2 serial interface address: h55e 10.7.95 qosc48 ? credit_c5_g2 serial interface address: h55f fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x11 always normal bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved
MVTX2803Ag data sheet semicmf.019 72 10.7.96 qosc49? credit_c6_g2 serial interface address: h560 10.7.97 qosc4a? credit_c7_g2 serial interface address: h561 qosc43 through qosc4arepresents the set of wfq parameters (see section 7.5) for gigabit port 2. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc43 corresponds to w0, and qosc4a corresponds to w7. in the 2g trunk configur ation, the sum of all values qosc43 through qosc4a must equal 128. classes wfq credit port g3 10.7.98 qosc4b ? credit_c0_g3 serial interface address: h562 see table below: bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: priority type. define one of the four qos mode of operation for port 3 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4 queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0
data sheet MVTX2803Ag 73 semicmf.019 10.7.99 qosc4 ? credit_c1_g3 serial interface address: h563 10.7.100 qosc4d ? credit_c2_g3 serial interface address: h564 10.7.101 qosc4e ? credit_c3_g3 serial interface address: h565 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) (0= do not send any frames if the xoff is on. (1= the p7-p2 frames can be sent even the xoff is on) bits [5:0] w1 - credit register. (default 4?h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x11 always normal bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved
MVTX2803Ag data sheet semicmf.019 74 10.7.102 qosc4f ? credit_c4_g3 serial interface address: h566 10.7.103 qosc50 ? credit_c5_g3 serial interface address: h567 10.7.104 qosc51? credit_c6_g3 serial interface address: h568 10.7.105 qosc52? credit_c7_g3 serial interface address: h569 qosc4b through qosc52 represents the set of wfq parameters (see section 7.5) for gigabit port 3. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc4b corresponds to w0, and qosc52 corresponds to w7. classes wfq credit port g4 10.7.106 qosc53 ? credit_c0_g4 serial interface address: h56a bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 4 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4
data sheet MVTX2803Ag 75 semicmf.019 see table below: 10.7.107 qosc54 ? credit_c1_g4 serial interface address: h56b queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) (0= do not send any frames if the xoff is on. (1= the p7-p2 frames can be sent even the xoff is on) bits [5:0] w1 -credit register. (default 4?h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal
MVTX2803Ag data sheet semicmf.019 76 10.7.108 qosc55 ? credit_c2_g4 serial interface address: h56c 10.7.109 qosc56 ? credit_c3_g4 serial interface address: h56d 10.7.110 qosc57 ? credit_c4_g4 serial interface address: h56e 10.7.111 qosc58 ? credit_c5_g4 serial interface address: h56f 10.7.112 qosc59? credit_c6_g4 serial interface address: h570 10.7.113 qosc5a? credit_c7_g4 serial interface address: h571 qosc53 through qosc5a represents the set of wfq parameters (see section 7.5) for gigabit port 4. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc53 corresponds to w0, and qosc5a corresponds to w7. in the 2g trunk configur ation, the sum of all values qosc53 through qosc5a must equal 128. bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved
data sheet MVTX2803Ag 77 semicmf.019 classes wfq credit port g5 10.7.114 qosc5b ? credit_c0_g5 serial interface address: h572 see table below: 10.7.115 qosc5c ? credit_c1_g5 serial interface address: h573 bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 5 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4 queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) (0= do not send any frames if the xoff is on. (1= the p7-p2 frames can be sent even the xoff is on) bits [5:0] w1 - credit register. (default 4?h04)
MVTX2803Ag data sheet semicmf.019 78 10.7.116 qosc5d ? credit_c2_g5 serial interface address: h574 10.7.117 qosc5e ? credit_c3_g5 serial interface address: h575 10.7.118 qosc5f ? credit_c4_g5 serial interface address: h576 10.7.119 qosc60 ? credit_c5_g5 serial interface address: h577 fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved
data sheet MVTX2803Ag 79 semicmf.019 10.7.120 qosc61? credit_c6_g5 serial interface address: h578 10.7.121 qosc62? credit_c7_g5 serial interface address: h579 qosc5b through qosc62 represents the set of wfq parameters (see section 7.5) for gigabit port 5. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc5b corresponds to w0, and qosc62 corresponds to w7. classes wfq credit port g6 10.7.122 qosc63 ? credit_c0_g6 serial interface address: h57a see table below: bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 6 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4 queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0
MVTX2803Ag data sheet semicmf.019 80 10.7.123 qosc64 ? credit_c1_g6 serial interface address: h57b 10.7.124 qosc65 ? credit_c2_g6 serial interface address: h57c 10.7.125 qosc66 ? credit_c3_g6 serial interface address: h57d bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) (0= do not send any frames if the xoff is on. (1= the p7-p2 frames can be sent even the xoff is on) bits [5:0] w1 - credit register. (default 4?h04) fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved
data sheet MVTX2803Ag 81 semicmf.019 10.7.126 qosc67 ? credit_c4_g6 serial interface address: h57e 10.7.127 qosc68 ? credit_c5_g6 serial interface address: h57f 10.7.128 qosc69? credit_c6_g6 serial interface address: h580 10.7.129 qosc6a? credit_c7_g6 serial interface address: h581 qosc63 through qosc6a represents the set of wfq parame ters (see section 7.5) for gigabit port 6. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc63 corresponds to w0, and qosc6a corresponds to w7. in the 2g trunk configur ation, the sum of all values qosc63 through qosc6a must equal 128. bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w6 - credit register. (default 5?h8) bits [7:6]: reserved bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved
MVTX2803Ag data sheet semicmf.019 82 classes wfq credit port g7 10.7.130 qosc6b ? credit_c0_g7 serial interface address: h582 10.7.131 qosc6c ? credit_c1_g7 serial interface address: h583 bits [5:0]: w0 - credit register for wfq. (default 6?h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 7 (default 2?00) 00 : option 1 01: option 2 10: option 3 11: option 4 queue p7 p6 p5 p4 p3 p2 p1 p0 option 1 bit [7:6] = 2?b00 delay bound be option 2 bit [7:6] = 2?b01 sp delay bound be option 3 bit [7:6] = 2?b10 sp wfq opition 4 bit [7:6] = 2?b11 wfq credit for wfq ? bit [5:0] w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 bits [7]: ? flow control allow during wfq scheme. (default 1?b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1?b1) (0= do not send any frames if the xoff is on. (1= the p7-p2 frames can be sent even the xoff is on) bits [5:0] w1 - credit register. (default 4?h04)
data sheet MVTX2803Ag 83 semicmf.019 10.7.132 qosc6d ? credit_c2_g7 serial interface address: h584 10.7.133 qosc6e ? credit_c3_g7 serial interface address: h585 10.7.134 qosc6f ? credit_c4_g7 serial interface address: h586 10.7.135 qosc70 ? credit_c5_g7 serial interface address: h587 fc_allow fc_be_only lost_ok egress- for dest fc_status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 101 (wfq only) always normal x 1 0 go to be queue if (src fc on) x11 always normal bits [5:0] w2 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w3 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w4 - credit register. (default 4?h04) bits [7:6]: reserved bits [5:0] w5 - credit register. (default 5?h8) bits [7:6]: reserved
MVTX2803Ag data sheet semicmf.019 84 10.7.136 qosc71? credit_c6_g7 serial interface address: h588 10.7.137 qosc72? credit_c7_g7 serial interface address: h589 qosc6b through qosc72 represents the set of wfq para meters (see section 7.5) for gigabit port 7. the granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. qosc6b corresponds to w0, and qosc72 corresponds to w7. class 6 shaper control port g0 10.7.138 qosc73 ? token_rate_g0 serial interface address: h58a 10.7.139 qosc74 ? token_limit_g0 serial interface address: h58b qosc73 and qosc74 correspond to parameters from section 7.6 on the shaper for ef traffic. qosc73 is an integer less than 64, with granularity 1. qosc74 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multiples of 16. qosc73 and qosc74 apply to gigabit port 0. register qosc39-credit_c6_g0 programs the peak rate. see qos application note for more information. class 6 shaper control port g1 10.7.140 qosc75 ? token_rate_g1 serial interface address: h58c bits [5:0] w6 - credit register. (default 5?h8) bits [5:0] w7 - credit register. (default 5?h10) bits [7:6]: reserved bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08) 1bits [7:0] bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0) bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08)
data sheet MVTX2803Ag 85 semicmf.019 10.7.141 qosc76 ? token_limit_g1 serial interface address: h58d qosc75 and qosc76 correspond to parameters from section 7.6 on the shaper for ef traffic. qosc75 is an integer less than 64, with granularity 1. qosc76 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multip les of 16. qosc75 and qosc76 apply to gigabit port 1. register qosc41-credit_c6_g1 programs the peak ra te. see qos application note for more information. class 6 shaper control port g2 10.7.142 qosc77 ? token_rate_g2 serial interface address: h58e 10.7.143 qosc78 ? token_limit_g2 serial interface address: h58f qosc77 and qosc78 correspond to parameters from section 7.6 on the shaper for ef traffic. qosc77 is an integer less than 64, with granularity 1. qosc78 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multip les of 16. qosc77 and qosc78 apply to gigabit port 2. register qosc49-credit_c6_g2 programs the peak ra te. see qos application note for more information. class 6 shaper control port g3 10.7.144 qosc79 ? token_rate_g3 serial interface address: h590 bits [7:0] bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0) bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08) bits [7:0] bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0) bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08)
MVTX2803Ag data sheet semicmf.019 86 10.7.145 qosc7a ? token_limit_g3 serial interface address: h591 qosc79 and qosc7a correspond to parameters from sectio n 7.6 on the shaper for ef traffic. qosc79 is an integer less than 64, with granularity 1. qosc7a is the programmed maximum value of the counter (maximum burst size). this value is expressed in multip les of 16. qosc79 and qosc7a apply to gigabit port 3. register qosc51-credit_c6_g3 programs the peak ra te. see qos application note for more information. class 6 shaper control port g4 10.7.146 qosc7b ? token_rate_g4 serial interface address: h592 10.7.147 qosc7c ? token_limit_g4 serial interface address: h593 qosc7b and qosc7c correspond to parameters from section 7.6 on the shaper for ef traffic. qosc7b is an integer less than 64, with granularity 1. qosc7c is the programmed maximum value of the counter (maximum burst size). this value is expressed in multip les of 16. qosc7b and qosc7c apply to gigabit port 4. register qosc59-credit_c6_g4 programs the peak ra te. see qos application note for more information. class 6 shaper control port g5 10.7.148 qosc7d ? token_rate_g5 serial interface address: h594 10.7.149 qosc7e ? token_limit_g5 serial interface address: h595 bits [7:0] bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0) bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08) bits [7:0] bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0) bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08) bits [7:0] bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0)
data sheet MVTX2803Ag 87 semicmf.019 qosc7d and qosc7e correspond to parameters from section 7.6 on the shaper for ef traffic. qosc7d is an integer less than 64, with granularity 1. qosc 7e is the programmed maximum value of the counter (maximum burst size). this value is expressed in multiples of 16. qosc7d and qosc7e apply to gigabit port 5. register qosc60-credit_c6_g5 programs t he peak rate. see qos application note for more information. class 6 shaper control port g6 10.7.150 qosc7f ? token_rate_g6 serial interface address: h596 10.7.151 qosc80 ? token_limit_g6 serial interface address: h597 qosc7f and qosc80 correspond to parameters from section 7.6 on the shaper for ef traffic. qosc7f is an integer less than 64, with granularity 1. qosc80 is the programmed maximum value of the counter (maximum burst size). this value is expressed in mult iples of 16. qosc7f and qosc80 apply to gigabit port 6. register qosc69-credit_c6_g6 programs the peak ra te. see qos application note for more information. class 6 shaper control port g7 10.7.152 qosc81 ? token_rate_g7 serial interface address: h598 10.7.153 qosc82 ? token_limit_g7 serial interface address: h599 qosc81 and qosc82 correspond to parameters from section 7.6 on the shaper for ef traffic. qosc81 is an integer less than 64, with granularity 1. qosc82 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multip les of 16. qosc81 and qosc82 apply to gigabit port 7. register qosc6f-credit_c6_g7 programs the peak rate . see qos application note for more information bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08) bits [7:0] bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0) bits [7:0] bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8?h08) bits [7:0] bytes allow to continue transmit out when regulated by shaper logic. (16byte/unit) (default: 8?hc0)
MVTX2803Ag data sheet semicmf.019 88 10.7.154 rdrc0 ? wred rate control 0 i 2 c address: h085, serial interface address: h59a accessed by serial interface and i 2 c (r/w) 10.7.155 rdrc1 ? wred rate control 1 i 2 c address: h086, serial interface address: h59b accessed by serial interface and i 2 c (r/w) 10.8 group 6 address - misc group 10.8.1 mii_op0 ? mii register option 0 i 2 c address: h0b1, serial interface address: h600 accessed by serial interface and i 2 c (r/w) 70 x rate y rate bits [7:4]: corresponds to the percentage x% in chapter 7. used for random early drop. granularity 6.25%. (default: 4?h8) bits[3:0]: corresponds to the percentage y% in chapter 7. used for random early drop. granularity 6.25%. (default: 4?he) 70 z rate b rate bits [7:4]: corresponds to the percentage z% in chapter 7. used for random early drop. granularity 6.25%.%. (default: 4?h6) bits[3:0]: corresponds to the best effort frame drop percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. used for random early drop. granularity 6.25%.%. (default: 4?h8) 76 5 4 0 hfc 1prst np vendor spc. reg addr bit [7]: ? half duplex flow control no default enable (do not use half duplex mode) 0 = half duplex flow control always enable 1 = half duplex flow control by negotiation bit[6]: link partner reset auto-negotiate disable
data sheet MVTX2803Ag 89 semicmf.019 10.8.2 mii_op1 ? mii register option 1 i 2 c address: h0b2, serial interface address: h601 accessed by serial interface and i 2 c (r/w) 10.8.3 fen ? feature register i 2 c address: h0b3, serial interface address: h602 accessed by serial interface and i 2 c (r/w) bit [5] ? next page enable 1: enable 0: disable bit[4:0]: vendor specified link status r egister address (null value means don?t use it) (default 00) 743 0 speed bit location duplex bit location bits[3:0]: duplex bit location in vendor specified register bits [7:4]: speed bit location in vendor specified register (default 00) 70 dml mii rp ip mul v-sp ds rc sc bits [0]: reserved bits[1]: reserved bit [2]: ? support ds ef code. (default 0) 0 ? disable 1 ? enable (all ports) when 101110 is detected in ds field (tos[7:2]), the frame priority is set for 110 and drop is set for 0. bit [3]: reserved bit [4]: reserved bit [5]: reserved bit [6]: 0: enable mii management state machine (default 0) 1: disable mii management state machine bit [7]: 0: enable using mct link list structure 1: disable using mct link list structure
MVTX2803Ag data sheet semicmf.019 90 10.8.4 miic0 ? mii command register 0 serial interface address:h603 accessed by serial interface (r/w) bit [7:0] mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 10.8.5 miic1 ? mii command register 1 serial interface address:h604 accessed by serial interface (r/w) bit [7:0] mii data [15:8] note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 10.8.6 miic2 ? mii command register 2 serial interface address:h605 accessed by serial interface (r/w) note: before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 10.8.7 miic3 ? mii command register 3 serial interface address:h606 accessed by serial interface (r/w) note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 70 mii op register address bits [4:0]: reg_ad ? register phy address bit [6:5] op ? operation code ?10? for read command and ?01? for write command 70 rdy valid phy address bits [4:0]: phy_ad ? 5 bit phy address bit [6] valid ? data valid from phy (read only) bit [7] rdy ? data is returned from phy (ready only)
data sheet MVTX2803Ag 91 semicmf.019 10.8.8 miid0 ? mii data register 0 serial interface address:h607 accessed by serial interface (ro) bit [7:0] mii data [7:0] 10.8.9 miid1 ? mii data register 0 serial interface address:h608 accessed by serial interface (ro) bit [7:0] mii data [15:8] 10.8.10 led mode ? led control i 2 c address:h0b4; serial interface address:h609 accessed by serial interface and i 2 c (r/w) 70 lpbk elpbk clock rate hold time se bit[1:0] ? sample hold time (default 2?b00) 2?b00- 8 msec 2?b01- 16 msec 2?b10- 32 msec 2?b11- 64 msec bit[3:2] ? led clock speed (serial mode) (default 2?b10) 2?b00- sclk/128 2?b01- sclk/256 2?b10- sclk/1024 2?b11- sclk/2048 ? led clock speed (parallel mode) (default 2?b10) 2?b00- sclk/1024 2?b01- sclk/4096 2?b10- sclk/2048 2?b11- sclk/8192
MVTX2803Ag data sheet semicmf.019 92 bit[5:4] led indicator out pattern (default 2?b11) 2?b00- normal output, led signals go straight out, no logical combina- tion 2?b01- 4 bi-color led mode 2?b10- 3 bi-color led mode 2?b11- programmable mode 1. normal mode: led_byteout_[7]:c ollision (col) led_byteout_[6]:full duplex (fdx) led_byteout_[5]:speed[1] (sp1) led_byteout_[4]:speed[0] (sp0) led_byteout_[3]:link (lnk) led_byteout_[2]:rx (rxd) led_byteout_[1]:tx (txd) led_byteout_[0]:flow control (fc) 2. 4 bi-color led mode led_byteout_[7]:col led_byteout_[6]:1000fdx led_byteout_[5]:1000hdx led_byteout_[4]:100fdx led_byteout_[3]:100hdx led_byteout_[2]:10fdx led_byteout_[1]:10hdx led_byteout_[0]:act note: all output qualified by link signal
data sheet MVTX2803Ag 93 semicmf.019 10.8.11 device mode i 2 c address h0b5; serial interface address:h60a accessed by serial interface and i 2 c (r/w) 10.8.12 checksum - eeprom checksum i 2 c address h0c5, serial interface address:h60b accessed by serial interface and i 2 c (r/w) 3. 3 bi-color led mode: led_byteout_[7]:col led_byteout_[6]:lnk led_byteout_[5]:fc led_byteout_[4]:spd1000 led_byteout_[3]:spd100 led_byteout_[2]:fdx led_byteout_[1]:hdx led_byteout_[0]:act note: all output qualified by link signal 4. programmable mode: led_byteout_[7]:link led_byteout_[6:0]:defined by the ledsig6 ~ ledsig0 program- mable registers. note: all output qualified by link signal bit[6]: reserved. must be '0' bit[7]: enable internal loop back. when this bit is set to '1' all ports work in internal loop back mode. for normal operation must be '0'. 7320 device id bit[2:0]: reserved bit [7:3]: device id (default 0). this is for stacking operation. this is the stack id for loop topology. bit [7:0]: (default 00)
MVTX2803Ag data sheet semicmf.019 94 10.8.13 led user 10.8.14 leduser0 i 2 c address h0bb, serial interface address:h60c accessed by serial interface and i 2 c (r/w) 10.8.15 leduser1 i 2 c address h0bc, serial interface address:h60d accessed by serial interface and i 2 c (r/w) before requesting that the mvtx2603ag updates the eeprom device, the correct checksum needs to be calculated and written into this checksum register. the checksum formula is: ff i 2 c register = 0 i = 0 after booting cicle the mvtx2603ag calculates the checksum. if the checksum is not zeroed the MVTX2803Ag does not start. 70 led user0 bit [7:0]: (default 00) content will send out by led serial logic 70 led user1 bit [7:0]: (default 00) content will send out by led serial logic
data sheet MVTX2803Ag 95 semicmf.019 10.8.16 leduser2/ledsig2 i 2 c address h0bd, serial interface address:h60e accessed by serial interface and i 2 c (r/w) in serial mode: in parallel mode: this register is used for programming the led pin ? led_byteout_[2] 10.8.17 eduser3/ledsig3 i 2 c address:h0be, serial interface address:h60f access by cpu, serial interface (r/w) in serial mode: in parallel mode: this register is us ed for programming the led pin - led_byteout_[3] 70 led user2 bit [7:0]: (default 00) content will be sent out by led serial shift logic 743 0 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0]: (default 4?h0) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4?h8) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[2] = and (all selected bits) 7 0 led user3 bit [7:0]: (default 8?h33) content will be sent out by led serial shift logic. 7 43 0 col fdx sp1 sp0 col fdx sp1 sp0
MVTX2803Ag data sheet semicmf.019 96 10.8.18 leduser4/ledsig4 i 2 c address:h0bf, serial interface address:h610 access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[4] bit [3:0]: (default 4?h3) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4?h3) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[3] = and (all selected bits) 7 0 led user4 bit [7:0] (default 8?h32) content will be sent out by led serial shift logic. 7 43 0 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0] (default 4?h2) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4?h3) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[4] = and (all selected bits)
data sheet MVTX2803Ag 97 semicmf.019 10.8.19 leduser5/ledsig5 i 2 c address:h0c0, serial interface address:h611 access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[5] 10.8.20 leduser6/ledsig6 i 2 c address:h0c1, serial interface address:h612 access by cpu, serial interface (r/w) in parallel mode: this register is us ed for programming the led pin - led_byteout_[6] 7 0 led user5 bit [7:0] (default 8?h20) content will be sent out by led serial shift logic. 7 43 0 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0] (default 4?h0) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4?h2) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[5] = and (all selected bits) 7 0 led user6 bit [7:0] (default 8?h40) content will be sent out by led serial shift logic. 7 43 0 col fdx sp1 sp0 col fdx sp1 sp0
MVTX2803Ag data sheet semicmf.019 98 10.8.21 leduser7/ledsig1_0 i 2 c address:h0c2, serial interface address:h613 access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[2] bit [3:0] (default 4?b0000) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4?b0100) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[6] = and (all selected bits), or the polarity of led_byteout_ [6] is controlled by ledsig1_0[3] 7 0 led user7 bit [7:0] (default 8?h61) content will be sent out by led serial shift logic. 7 43 0 gp rx tx fc p6 rx tx fc bit [7] (default 1?b0) ? global output polarity: this bit c ontrols the output polarity of all led_byteout_ and led_port_sel pins. 0: no invert polarity - (led_by teout_[7:0] are high activated, led_port_sel[9:0] are low activated) 1: invert polarity - (led_byteout_[7:0] are low activated, led_port_sel[9:0] are high activated) bit [6:4] (default 3?b110) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_by teout_[6] = or (all selected bits) bit[3] (default 1?b0) polarity control of led_byteout_[6] 0: not invert 1: invert
data sheet MVTX2803Ag 99 semicmf.019 10.8.22 miinp0 ? mii next page data register 0 i 2 c address:h0c3, serial interface address:h614 access by cpu and serial interface only (r/w) 10.8.23 miinp1 ? mii next page data register 1 i 2 c address:h0c4, serial interface address:h615 access by cpu and serial interface only (r/w) 10.9 group f address - cpu access group 10.9.1 gcr-global control register serial interface address: hf00 accessed by serial interface. (r/w) bit [2:0] (default 3?b001) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[0] = or (all selected bits) bit [7:0] mii next page data [7:0] bit [7:0] mii next page data [15:8] 70 init reset bist sr sc bit [0]: store configuration (default = 0) write ?1? followed by ?0? to store configuration into external eeprom bit[1]: store configuration and reset (default = 0) write ?1? to store configuration into external eeprom and reset chip bit[2]: start bist (default = 0) write ?1? followed by ?0? to start the device?s built-in self-test. the result is found in the dcr register. bit[3]: soft reset (default = 0) write ?1? to reset the chip bit[4]: reserved bit[5:7]: reserved
MVTX2803Ag data sheet semicmf.019 100 10.9.2 dcr-device status and signature register serial interface address: hf01 accessed by serial interface. (ro) 10.9.3 dcr01-giga port status serial interface address: hf02 accessed by serial interface. (ro) 70 revision signature re binp br bw bit [0]: 1 - busy writing configuration to i 2 c 0 ? not busy writing configuration to i 2 c bit[1]: 1 - busy reading configuration from i 2 c 0 ? not busy reading configuration from i 2 c bit[2]: 1 - bist in progress 0 - bist not running bit[3]: 1 - ram error 0 ? ram ok bit[5:4]: device signature 00 ? 4 ports device, non-management mode 01 ? 8 ports device, non-management mode 10 ? 4 ports device, management mode possible (need to install cpu) 11 - 8 ports device, management mode possible (need to install cpu) bit [7:6]: revision 7 3210 cic giga1 giga0 bit [1:0]: giga port 0 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs
data sheet MVTX2803Ag 101 semicmf.019 10.9.4 dcr23-giga port status serial interface address: hf03 accessed by cpu and serial interface. (ro) 10.9.5 dcr45-giga port status serial interface address: hf04 accessed by cpu and serial interface. (ro) bit[3:2] giga port 1 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit [7] chip initialization completed note: dcr01[7], dcr23[7], dcr45[7] and dcr67[7] have the same function. 7 3210 cic giga3 giga2 bit [1:0]: giga port 2 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit[3:2] giga port 3 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit [7] chip initialization completed 73210 cic giga5 giga4
MVTX2803Ag data sheet semicmf.019 102 10.9.6 dcr67-giga port status serial interface address: hf05 accessed by cpu and serial interface. (ro) bit [1:0]: giga port 4 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit[3:2] giga port 5 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit [7] chip initialization completed 7 3210 cic giga7 giga6 bit [1:0]: giga port 6 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit[3:2] giga port 7 strap option 00 ? 100mb mii mode 01 ? 2g mode 10 ? gmii 11 ? pcs bit [7] chip initialization completed
data sheet MVTX2803Ag 103 semicmf.019 10.9.7 dpst ? device port status register serial interface address:hf06 accessed by cpu and serial interface (r/w) 10.9.8 dtst ? data read back register serial interface address: hf07 accessed by cpu and serial interface (ro) this register provides various internal information as select ed in dpst bit[2:0] bit[2:0]: read back index register. this is used for selecting what to read back from dtst. (default 00) 3?b000 - port 0 operating mode and negotiation status 3?b001 - port 1 operating mode and negotiation status 3?b010 - port 2 operating mode and negotiation status 3?b011 - port 3 operating mode and negotiation status 3?b100 - port 4 operating mode and negotiation status 3?b101 - port 5 operating mode and negotiation status 3?b110 - port 6 operating mode and negotiation status 3?b111 - port 7 operating mode and negotiation status 7 0 md infodet sigdet giga lnkdn fe fdpx fc_en bit[0]: flow control enabled bit[1]: full duplex port bit[2]: fast ethernet port (if not giga) bit[3]: link is down bit[4]: giga port bit[5]: signal detect (when pcs interface mode) bit[6]: pipe signal detected (pipe mode only) bit[7]: module detected (for hot swap purpose)
MVTX2803Ag data sheet semicmf.019 104 11.0 bga and ball signal description 11.1 bga views 123456789101112131415161718192021222324252627282930 avd d nc9 sca nen lb_d [0] lb_d [4] lb_d [5] lb_d [10] lb_d [16] lb_d [19] lb_d [26] lb_d [31] lb_d [32] lb_d [36] lb_d [40] lb_d [45] s_cl k lb_d [60] lb_a [3] lb_a [7] lb_a [11] lb_a [15] b_a[ 16] b_a[ 12] b_a[ 7] b_a[ 2] b_oe # b_d[ 27] b_d[ 26] nc4 nc3 dev_ cf[0] la_d [0] nc7 lb_d [1] lb_d [3] lb_d [6] lb_d [12] lb_d [17] lb_d [20] lb_d [28] lb_c s0# lb_d [33] lb_d [37] lb_d [41] lb_d [47] lb_d [54] lb_d [58] lb_d [62] lb_a [6] lb_a [10] lb_a [13] b_a[ 17] b_a[ 13] b_a[ 8] b_a[ 3] b_w e# b_d[ 30] dev_ cfg[ nc5 b_d[2 5] la_d [1] la_c lk la_d [3] nc6 lb_d [2] lb_d [8] lb_d [15] lb_d [18] lb_d [21] lb_d [29] lb_r w# lb_d [34] lb_d [39] lb_d [43] lb_d [48] lb_d [52] lb_d [57] lb_d [61] lb_a [4] lb_a [8] lb_a [12] b_a[ 18] b_a[ 14] b_a[ 11] b_a[ 5] b_a[ 4] b_d[ 28] avd d b_cl k b_d[2 2] la_d [2] la_d [5] la_d [9] nc8 lb_c lk lb_d [9] lb_d [13] lb_d [23] lb_d [22] lb_d [24] lb_d [25] lb_d [35] lb_d [42] lb_d [44] lb_d [50] lb_d [51] lb_d [55] lb_d [63] lb_a [14] lb_a [18] lb_a [16] lb_a [19] b_a[ 9] b_a[ 10] b_ad sc# nc2 b_d[ 29] b_d[ 24] b_d[ 18] b_d[2 1] la_d [8] la_d [7] la_d [6] la_d [4] agn d lb_d [7] lb_d [14] lb_d [11] lb_d [27] lb_d [30] lb_c s1# lb_d [38] lb_d [46] lb_d [49] lb_d [53] lb_d [56] lb_d [59] lb_a [5] lb_a [9] lb_a [17] lb_a [20] b_a[ 15] b_a[ 6] b_d[ 31] agn d b_d[ 17] b_d[ 23] b_d[ 19] b_d[ 16] b_d[1 4] la_d [10] la_d [11] la_d [12] la_d [13] la_d [14] vss vss vdd vdd vd33 vd33 vd33 vss vss vd33 vd33 vd33 vdd vdd vss vss nc1 b_d[ 9] b_d[ 10] b_d[ 11] b_d[1 2] la_d [15] la_d [16] la_d [19] la_d [18] la_d [17] vdd vdd b_d[ 20] b_d[ 4] b_d[ 3] b_d[ 6] b_d[7] la_d [20] la_d [21] la_d [22] la_d [29] la_d [24] b_d[ 15] b_d[ 8] p_in t# b_d[ 1] b_d[2] la_d [23] la_d [25] la_d [26] la_d [27] la_d [31] vdd vdd b_d[ 13] p_a[ 1] p_a[ 2] p_w e# p_rd# la_d [28] la_d [30] la_c s0# la_d [37] la_d [33] vdd vdd b_d[ 5] p_d[ 15] p_d[ 11] p_d[ 12] p_d[1 3] l la_c s1# la_r w# la_d [32] la_d [46] la_d [41] p_cs # p_d[ 14] p_d[ 7] p_d[ 8] p_d[1 0] la_d [34] la_d [35] la_d [36] la_d [53] la_d [48] vd33 vd33 p_a[ 0] b_d[ 0] p_d[ 3] p_d[ 4] p_d[5] la_d [38] la_d [40] la_d [42] la_d [61] la_d [56] vd33 vss vss vss vss vss vss vd33 p_d[ 6] p_d[ 9] p_d[ 0] p_d[ 1] p_d[2] la_d [43] la_d [44] la_d [45] la_a [4] la_d [39] vd33 vss vss vss vss vss vss vd33 t_d[ 15] t_d[ 11] t_d[ 12] t_d[ 13] t_d[14 ] la_d [49] la_d [50] la_d [51] la_d [52] la_d [47] vss vss vss vss vss vss vss vss t_d[ 10] t_d[ 5] t_d[ 7] t_d[ 8] t_d[9] la_d [58] la_d [57] la_d [55] la_d [54] la_a [7] vss vss vss vss vss vss vss vss t_d[ 6] t_d[ 4] t_d[ 2] t_d[ 1] t_d[0] la_d [63] la_d [62] la_d [60] la_d [59] la_a [11] vd33 vss vss vss vss vss vss vd33 s_r st# t_d[ 3] tmo de[1] tmo de[0] reso ut# la_a [6] la_a [5] la_a [3] la_a [14] la_a [18] vd33 vss vss vss vss vss vss vd33 g7_ rxd[ g7_r xer lesy no# le_c lk0 le_do la_a [10] la_a [9] la_a [8] la_a [20] g0_t xd[1] vd33 vd33 g7_ rxd[ g7_r xd[1] g7_r xdv g7_r xd[6] g7_rx d[5] la_a [15] la_a [13] la_a [12] g0_c rs/l g0_t xd[4] g7_t xd[6] g7_t xen g7_r xd[4] g7_r xd[2] g7_rx d[0] la_a [19] la_a [17] la_a [16] gre fc[0] g0_t xd[7] vdd vdd g7_t xd[0] g7_t xd[3] g7_c ol g7_r xclk miitx ck[7] miitx ck[0] g0_t xd[2] g0_t xd[0] g0_t xclk g0_t xe vdd vdd g6_ rxd[ g7_t xer g7_t xd[7] g7_t xd[5] g7_tx d[4] g0_r xclk g0_t xd[5] g0_t xd[3] g0_r xd[2] g0_r xd[6] g6_r xd[2] g6_r xd[4] g7_t xd[2] g7_t xd[1] g7_c rs/l g0_r xd[0] g0_t xen g0_c ol g0_t xd[6] g0_ rx vss vdd g6_ rxd[ g6_r xer g7_t xclk gre fc[7] g6_rx dv g0_r xd[5] g0_r xd[4] g0_r xd[3] g0_r xd[1] g1_t xd[0] vss vdd vdd vdd vd33 vd33 vd33 vss vss vd33 vd33 vd33 vdd vdd vss vss g6_t xd[7] g6_r xd[6] g6_r xd[5] g6_r xd[3] g6_rx d[1] g0_r xd[7] g0_r xer gre fc[1] g1_r xd[2] g1_r xd[5] g1_r xd[7] g2_t xd[0] g2_t xd[7] g2_r xd[2] g2_r xd[4] g2_r xd[5] g3_t xd[1] g3_t xd[6] g3_c ol g3_r xd[3] g3_r xd[6] ind_ cm g3_r xd[4] g3_r xer g4_t xd[3] g4_r xd[1] g4_r xd[4] g5_t xd[2] g5_t xd[4] g5_t xer g5_r xd[5] g6_r xclk g6_t xd[6] g6_c ol g6_tx er g1_t xd[1] g1_t xclk g1c rs/l g1_t xd[7] g2_t xclk g1_r xd[4] g2_t xd[4] g2_t xd[3] g2_r xd[3] g2_r xclk g2_r xd[7] g2_r xer g3_t xen g3_r xd[0] g3_r xd[5] g3_r xd[7] gre fc[4] m_m dio g4_t xd[1] g4_r xd[5] g4_r xd[6] g4_r xd[7] g5_c rs/l g5_t xd[5] miitx ck[5] g5_r xd[1] g6_t xd[3] g6_t xd[4] g6_t xen g6_tx d[5] g1_t xd[2] g1_t xd[3] miitx ck[1] g1_r xd[0] g1_r xclk g2c rs/l miitx ck[2] g2_t xen g2_r xd[1] g2_r xdv g3_t xclk g3_t xd[3] g3_t xd[5] g3_r xclk g3_r xd[2] g3_r xdv g4_t xclk g4_t xd[4] g4_t xd[6] g4_t xer g4_r xclk g4_r xdv g4_r xer g5_t xd[3] g5_t xen g5_r xd[3] g5_r xd[6] g6_t xd[1] g6_t xd[2] g6_tx clk g1_t xd[5] g1_t xd[4] g1_t xer g1_c ol g1_r xd[6] gre fc[2] g2_t xd[2] g2_t xd[6] g2_r xd[0] g2_r xd[6] gre fc[3] g3_t xd[2] miitx ck[3] g3_t xer g3_r xd[1] m_m dc g4_t xd[0] g4_t xd[5] g4_t xd[7] g4_r xd[0] g4_c ol gre fc[5] g5_t xd[0] g5_t xd[6] g5_r xd[0] g5_c ol g5_r xd[4] g5_r xer g6_c rs/l g6_tx d[0] ak g1_t xd[6] g1_t xen g1_r xd[1] g1_r xd[3] g1_r xdv g1_r xer g2_t xd[1] g2_t xd[5] g2_t xer g2_c ol g3_c rs/l g3_t xd[0] g3_t xd[4] g3_t xd[7] cm_ clk g4c rs/l g4_t xd[2] miitx ck[4] g4_t xen g4_r xd[2] g4_r xd[3] g5_t xclk g5_t xd[1] g5_t xd[7] g5_r xd[2] g5_r xclk g5_r xd[7] g5_r xdv miitx ck[6] gref c[6] 123456789101112131415161718192021222324252627282930
data sheet MVTX2803Ag 105 semicmf.019 11.2 power and ground distribution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a vdd nc9 sca nen lb_d [0] lb_d [4] lb_d [5] lb_d [10] lb_d [16] lb_d [19] lb_d [26] lb_d [31] lb_d [32] lb_d [36] lb_d [40] lb_d [45] s_cl k lb_d [60] lb_a [3] lb_a [7] lb_a [11] lb_a [15] b_a[ 16] b_a[ 12] b_a[ 7] b_a[ 2] b_oe # b_d[ 27] b_d[ 26] nc4 nc3 dev_c f[0] la_d [0] nc7 lb_d [1] lb_d [3] lb_d [6] lb_d [12] lb_d [17] lb_d [20] lb_d [28] lb_c s0# lb_d [33] lb_d [37] lb_d [41] lb_d [47] lb_d [54] lb_d [58] lb_d [62] lb_a [6] lb_a [10] lb_a [13] b_a[ 17] b_a[ 13] b_a[ 8] b_a[ 3] b_w e# b_d[ 30] dev_ cfg[ nc5 b_d[ 25] la_d[1] la_c lk la_d [3] nc6 lb_d [2] lb_d [8] lb_d [15] lb_d [18] lb_d [21] lb_d [29] lb_r w# lb_d [34] lb_d [39] lb_d [43] lb_d [48] lb_d [52] lb_d [57] lb_d [61] lb_a [4] lb_a [8] lb_a [12] b_a[ 18] b_a[ 14] b_a[ 11] b_a[ 5] b_a[ 4] b_d[ 28] avd d b_cl k b_d[ 22] la_d[2] la_d [5] la_d [9] nc8 lb_c lk lb_d [9] lb_d [13] lb_d [23] lb_d [22] lb_d [24] lb_d [25] lb_d [35] lb_d [42] lb_d [44] lb_d [50] lb_d [51] lb_d [55] lb_d [63] lb_a [14] lb_a [18] lb_a [16] lb_a [19] b_a[ 9] b_a[ 10] b_ad sc# nc2 b_d[ 29] b_d[ 24] b_d[ 18] b_d[ 21] la_d[8] la_d [7] la_d [6] la_d [4] agn d lb_d [7] lb_d [14] lb_d [11] lb_d [27] lb_d [30] lb_c s1# lb_d [38] lb_d [46] lb_d [49] lb_d [53] lb_d [56] lb_d [59] lb_a [5] lb_a [9] lb_a [17] lb_a [20] b_a[ 15] b_a[ 6] b_d[ 31] agn d b_d[ 17] b_d[ 23] b_d[ 19] b_d[ 16] b_d[ 14] la_d[1 0] la_d [11] la_d [12] la_d [13] la_d [14] vss vss vdd vdd vd33 vd33 vd33 vss vss vd33 vd33 vd33 vdd vdd vss vss nc1 b_d[ 9] b_d[ 10] b_d[ 11] b_d[ 12] la_d[1 5] la_d [16] la_d [19] la_d [18] la_d [17] vdd vdd b_d[ 20] b_d[ 4] b_d[ 3] b_d[ 6] b_d[ 7] la_d[2 0] la_d [21] la_d [22] la_d [29] la_d [24] b_d[ 15] b_d[ 8] p_in t# b_d[ 1] b_d[ 2] la_d[2 3] la_d [25] la_d [26] la_d [27] la_d [31] vdd vdd b_d[ 13] p_a[ 1] p_a[ 2] p_w e# p_rd # la_d[2 8] la_d [30] la_c s0# la_d [37] la_d [33] vdd vdd b_d[ 5] p_d[ 15] p_d[ 11] p_d[ 12] p_d[ 13] l la_cs 1# la_r w# la_d [32] la_d [46] la_d [41] p_cs # p_d[ 14] p_d[ 7] p_d[ 8] p_d[ 10] la_d[3 4] la_d [35] la_d [36] la_d [53] la_d [48] vd33 vd33 p_a[ 0] b_d[ 0] p_d[ 3] p_d[ 4] p_d[ 5] la_d[3 8] la_d [40] la_d [42] la_d [61] la_d [56] vd33 vss vss vss vss vss vss vd33 p_d[ 6] p_d[ 9] p_d[ 0] p_d[ 1] p_d[ 2] la_d[4 3] la_d [44] la_d [45] la_a [4] la_d [39] vd33 vss vss vss vss vss vss vd33 t_d[ 15] t_d[ 11] t_d[ 12] t_d[ 13] t_d[ 14] la_d[4 9] la_d [50] la_d [51] la_d [52] la_d [47] vss vss vss vss vss vss vss vss t_d[ 10] t_d[ 5] t_d[ 7] t_d[ 8] t_d[ 9] la_d[5 8] la_d [57] la_d [55] la_d [54] la_a [7] vss vss vss vss vss vss vss vss t_d[ 6] t_d[ 4] t_d[ 2] t_d[ 1] t_d[ 0] la_d[6 3] la_d [62] la_d [60] la_d [59] la_a [11] vd33 vss vss vss vss vss vss vd33 s_rs t# t_d[ 3] tmo de[1] tmo de[0] res out# la_a[6] la_a [5] la_a [3] la_a [14] la_a [18] vd33 vss vss vss vss vss vss vd33 g7_r xd[7] g7_r xer lesy no# le_c lk0 le_d o la_a[1 0] la_a [9] la_a [8] la_a [20] g0_t xd[1] vd33 vd33 g7_r xd[3] g7_r xd[1] g7_r xdv g7_r xd[6] g7_r xd[5] la_a[1 5] la_a [13] la_a [12] g0_c rs/l g0_t xd[4] g7_t xd[6] g7_t xen g7_r xd[4] g7_r xd[2] g7_r xd[0] la_a[1 9] la_a [17] la_a [16] gre fc[0] g0_t xd[7] vdd vdd g7_t xd[0] g7_t xd[3] g7_c ol g7_r xclk miitx ck[7] miitxc k[0] g0_t xd[2] g0_t xd[0] g0_t xclk g0_t xer vdd vdd g6_r xd[7] g7_t xer g7_t xd[7] g7_t xd[5] g7_t xd[4] g0_rx clk g0_t xd[5] g0_t xd[3] g0_r xd[2] g0_r xd[6] g6_r xd[2] g6_r xd[4] g7_t xd[2] g7_t xd[1] g7_c rs/l g0_rx d[0] g0_t xen g0_c ol g0_t xd[6] g0_r xdv vss vdd g6_r xd[0] g6_r xer g7_t xclk gre fc[7] g6_r xdv g0_rx d[5] g0_r xd[4] g0_r xd[3] g0_r xd[1] g1_t xd[0] vss vdd vdd vdd vd33 vd33 vd33 vss vss vd33 vd33 vd33 vdd vdd vss vss g6_t xd[7] g6_r xd[6] g6_r xd[5] g6_r xd[3] g6_r xd[1] g0_rx d[7] g0_r xer gre fc[1] g1_r xd[2] g1_r xd[5] g1_r xd[7] g2_t xd[0] g2_t xd[7] g2_r xd[2] g2_r xd[4] g2_r xd[5] g3_t xd[1] g3_t xd[6] g3_c ol g3_r xd[3] g3_r xd[6] ind_ cm g3_r xd[4] g3_r xer g4_t xd[3] g4_r xd[1] g4_r xd[4] g5_t xd[2] g5_t xd[4] g5_t xer g5_r xd[5] g6_r xclk g6_t xd[6] g6_c ol g6_t xer g1_tx d[1] g1_t xclk g1c rs/l g1_t xd[7] g2_t xclk g1_r xd[4] g2_t xd[4] g2_t xd[3] g2_r xd[3] g2_r xclk g2_r xd[7] g2_r xer g3_t xen g3_r xd[0] g3_r xd[5] g3_r xd[7] gre fc[4] m_m dio g4_t xd[1] g4_r xd[5] g4_r xd[6] g4_r xd[7] g5_c rs/l g5_t xd[5] miitx ck[5] g5_r xd[1] g6_t xd[3] g6_t xd[4] g6_t xen g6_t xd[5] g1_tx d[2] g1_t xd[3] miitx ck[1] g1_r xd[0] g1_r xclk g2c rs/l miitx ck[2] g2_t xen g2_r xd[1] g2_r xdv g3_t xclk g3_t xd[3] g3_t xd[5] g3_r xclk g3_r xd[2] g3_r xdv g4_t xclk g4_t xd[4] g4_t xd[6] g4_t xer g4_r xclk g4_r xdv g4_r xer g5_t xd[3] g5_t xen g5_r xd[3] g5_r xd[6] g6_t xd[1] g6_t xd[2] g6_t xclk g1_tx d[5] g1_t xd[4] g1_t xer g1_c ol g1_r xd[6] gre fc[2] g2_t xd[2] g2_t xd[6] g2_r xd[0] g2_r xd[6] gre fc[3] g3_t xd[2] miitx ck[3] g3_t xer g3_r xd[1] m_m dc g4_t xd[0] g4_t xd[5] g4_t xd[7] g4_r xd[0] g4_c ol gre fc[5] g5_t xd[0] g5_t xd[6] g5_r xd[0] g5_c ol g5_r xd[4] g5_r xer g6_c rs/l g6_t xd[0] ak g1_tx d[6] g1_t xen g1_r xd[1] g1_r xd[3] g1_r xdv g1_r xer g2_t xd[1] g2_t xd[5] g2_t xer g2_c ol g3_c rs/l g3_t xd[0] g3_t xd[4] g3_t xd[7] cm_ clk g4c rs/l g4_t xd[2] miitx ck[4] g4_t xen g4_r xd[2] g4_r xd[3] g5_t xclk g5_t xd[1] g5_t xd[7] g5_r xd[2] g5_r xclk g5_r xd[7] g5_r xdv miitx ck[6] gre fc[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MVTX2803Ag data sheet semicmf.019 106 11.3 ball- signal descriptions all pins are cmos type; all input pins are 5 volt tolerance, and all output pins are 3.3 cmos drive. ball no(s) symbol i/o description k27, l27, k30, k29, k28 p_data[15:11] i/o -ts with pull up not used ? leave unconnected l30 p_data[10] i/o ? ts with pull up trunk enable external pull up or unconnected? disable trunk group 0 and 1 external pull down ? enable trunk group 0 and 1 see register trunk0_mode for port selection and trunk enable. n27 p_data[9] i/o ? ts with pull up trunk enable external pull up or unconnected ? disable trunk group 2 and 3 external pull down ? enable trunk group 2 and 3 see register trunk1_mode for port selection and trunk enable. l29, l28, n26, m30, m29, m28, n30, n29, n28 p_data[8:0] i/o ? ts with pull up bootstrap function ? see bootstrap section j28 p_a[2] input not used ? leave unconnected h28 p_int# output not used ? leave unconnected i 2 c interface (0) note: in unmanaged mode, use i 2 c and serial control interface to configure the system j27 scl output i 2 c data clock m26 sda i/o-ts with pull up i 2 c data i/o serial control interface j29 ps_strobe i nput with weak internal pull up serial strobe pin l26 ps_do input with weak internal pull up serial data input j30 ps_di (autofd) output with pull up serial data output (autofd) frame buffer interface u1, u2, n4, u3, u4, t1, t2, n5, t3, t4, m4, r4, r3, r2, r1, m5, r5, l4, p3, p2, p1, n3, l5, n2, p5, n1, k4, m3, m2, m1, k5, l3, j5, k2, h4, k1, j4, j3, j2, h5, j1, h3, h2, h1, g3, g4, g5, g2, g1, f5, f4, f3, f2, f1, d3, e1, e2, e3, d2., e4, c3, d1, c1, b2 la_d[63:0] i/o-ts with pull up frame bank a? data bit [63:0]
data sheet MVTX2803Ag 107 semicmf.019 aa1, v5, aa2, aa3, y1, v4, y2, y3, u5, w1, w2, w3, t5, v1, v2, p4, v3 la_a[19:3] output frame bank a ? address bit [19:3] w4 la_a[20] output with pull up frame bank a ? address bit [20] c2 la_clk output frame bank a clock input k3 la_cs0# output with pull up frame bank a low portion chip selection l1 la_cs1# output with pull up frame bank a high portion chip selection l2 la_rw# output with pull up frame bank a read/write d18, b18, c18, a17, e17, b17, c17, e16, d17, b16, e15, c16, d16, d15, e14, c15, b15, e13, a15, d14, c14, d13, b14, a14, c13, e12, b13, a13, d12, c12, b12, a12, a11, e10, c10, b10, e9, a10, d11, d10, d8, d9, c9, b9, a9, c8, b8, a8, c7, e7, d7, b7, e8, a7, d6, c6, e6, b6, a6, a5, b5, c5, b4,a4 lb_d[63:0] i/o-ts with pull up. frame bank b? data bit [63:0] d22, d20, e20, d21, a21, d19, b21, c21, a20, b20, e19, c20, a19, b19, e18, c19, a18 lb_a[19:3] output frame bank b ? address bit [19:3] e21 lb_a[20] output with pull up frame bank b ? address bit [20] d5 lb_clk output frame bank b clock input b11 lb_cs0# output with pull up fr ame bank b low portion chip selection e11 lb_cs1# output with pull up fr ame bank b high portion chip selection c11 lb_rw# output with pull up frame bank b read/write switch database interface ball no(s) symbol i/o description
MVTX2803Ag data sheet semicmf.019 108 e24,b27, d27, c27, a27, a28, b30, d28, e27, c30, d30, g26, e28, d29, e26, e29, h26, e30, j26, f30, f29, f28, f27, h27, g30, g29, k26, g27, g28, h30, h29, m27 b_d[31:0] i/o-ts with pull up switch database domain ? data bit [31:0] c22, b22, a22, e22, c23, b23, a23, c24, d24, d23, b24, a24, e23, c25, c26, b25, a25 b_a[18:2] output switch database address (512k) ? address bit [18:2] c29 b_clk output switch database clock input d25 b_adsc# output with pull up switch database address status control b26 b_we# output with pull up switch database write chip select a26 b_oe# output with pull up switch database read chip select mii management interface aj16 m_mdc output mii management data clock ? (common for all mii ports [7:0]) ag18 m_mdio i/o-ts with pull up mii management data i/o ? (common for all mii ports ?[7:0])) 2.5mhz gmii / mii interface (193) gigabit ethernet access port ad29, ak30, aj22, ag17, aj11, aj6, af3,aa4 gref_clk [7:0] input w/ pull up gigabit reference clock ak15 cm_clk input w/ pull up common clock shared by port g[7:0] af17 ind/cm input w/ pull up 1: select gref_clk[7:0] as clock 0: select cm_clk as clock for all ports aa30, ak29, ag25, ak18, aj13, ah7, ah3, ab1 mii tx clk[7:0] input w/ pull up ball no(s) symbol i/o description
data sheet MVTX2803Ag 109 semicmf.019 v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af 5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1 , ae2, ae3, ac4, ae4, ad1 g7_rxd[7:0] g6_rxd[7:0] g5_rxd[7:0] g4_rxd[7:0] g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[7:0] port ? receive data bit [7:0] w28, ad30, ak28, ah22, ah16, ah10, ak5, ad5 g[7:0]_rx_dv input w/ pull down g[7:0]port ? receive data valid v27, ad27, aj28, ah23, af19, ag12, ak6, af2 g[7:0]_rx_er input w/ pull up g[7:0]port ? receive error ac30, aj29, ag23, ak16, ak11, ah6, ag3, y4 g[7:0]_crs/lin k input w/ pull down g[7:0]port ? carrier sense aa28, af29, aj26, aj21, af14, ak10, aj4, ad3 g[7:0]_col input w/ pull up g[7: 0]port ? collision detected aa29, af27, ak26, ah21, ah14, ag10, ah5, ac1 g[7:0]_rxclk input w/ pull up g[7:0]port ? receive clock ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g7_txd[7:0] g6_txd[7:0] g5_txd[7:0] g4_txd[7:0] g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[7:0]port ? transmit data bit [7:0] y27, ag29, ah25, ak19, ag13, ah8, ak2, ad2 g[7:0]_tx_en output w/ pull up g[7:0]port ? transmit data enable ab27, af30, af25, ah20, aj14, ak9, aj3, ab5 g[7:0]_tx_er output w/ pull up g[7:0]port ? transmit error ad28, ah30, ak22, ah17, ah11, ag5, ag2, ab4 g[7:0]_ txclk output g[7:0]port ? gigabit transmit clock ball no(s) symbol i/o description
MVTX2803Ag data sheet semicmf.019 110 pma interface (193) gigabit ethernet access port (pcs) ad29, ak30, aj22, ag17, aj11, aj6, af3,aa4 gref_clk [7:0] input w/ pull up gigabit reference clock ak15 cm_clk input w/ pull up common clock shared by port g[7:0] af17 ind/cm input w/ pull up 1: select gref_clk[7:0] as clock 0: select cm_clk as clock for all port v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g7_rxd[7:0] g6_rxd[7:0] g5_rxd[7:0] g4_rxd[7:0] g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[7:0]po rt ? pma receive data bit [ 7:0 ] w28, ad30, ak28, ah22, ah16, ah10, ak5, ad5 g[7:0]_rx_d[8] input w/ pull down g[7:0]port ? pma receive data bit [ 8 ] v27, ad27, aj28, ah23, af19, ag12, ak6, af2 g[7:0]_rx_d[9] input w/ pull up g[ 7:0]port ? pma receive data bit [ 9 ] aa28, af29, aj26, aj21, af14, ak10, aj4, ad3 g[7:0]_rxclk1 input w/ pull up g[7:0]port ? pma receive clock 1 aa29, af27, ak26, ah21, ah14, ag10, ah5, ac1 g[7:0]_rxclk0 input w/ pull up g[7:0]port ? pma receive clock 0 ball no(s) symbol i/o description
data sheet MVTX2803Ag 111 semicmf.019 ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g7_txd[7:0] g6_txd[7:0] g5_txd[7:0] g4_txd[7:0] g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[7:0]port ? pma transmit data bit [ 7:0 ] 2y27, ag29, ah25, ak19, ag13, ah8, ak2, ad2 3g[7:0]_txd[8] 4output w/ pull up 5g[7:0]port ? pma transmit data bit [ 8 ] ab27, af30, af25, ah20, aj14, ak9, aj3, ab5 g[7:0]_tx_d[9] output w/ pull up g[7:0]port ? pma transmit data bit [ 9 ] ad28, ah30, ak22, ah17, ah11, ag5, ag2, ab4 g[7:0]_ txclk output g[7:0]port ? pma gigabit transmit clock test facility (3) u29 t_mode0 i/o-ts with pull up test ? set upon reset, and provides nand tree test output during test mode use external pull up for normal operation u28 t_mode1 i/o-ts with pull up test ? set upon reset, and provides nand tree test output during test mode use external pull up for normal operation a3 scan_en input with pull down enable test mode for normal operation leave it unconnected led interface (serial and parallel) r28, t26, r27, t27, u27, t28, t29, t30 t_d[7:0]/ le_pd[7:0] output while resetting, t_d[7,0] are in input mode and are used as strapping pins. internal pull up le_pd - parallel led data [7:0] p26, p30, p29, p28, p27, r26, r30, r29 t_d[15:8]/ le_pt[7:0] output while resetting, t_d[15:8] are in input mode and are used as strapping pins. internal pull up led_pr[7:0] ? parallel led port selection [7:0] ball no(s) symbol i/o description
MVTX2803Ag data sheet semicmf.019 112 v29 le_clk0/ le_pt[8] output le_clk0 ? led serial interface output clock le_pt[8] ? parallel led port sel [8] v30 led_blink/ le_do/ le_pt[9] output while resetting, led-blink is in input mode and is used as strapping pin. 1: no blink, 0: blink. internal pull up. le_do - led serial data output stream le_pt[9] ? parallel led port sel [9] v28 led_pm/ le_synco# output with pull up while resetting, led_pm is in input mode and is used as strapping pin. internal pull up. 1: enable parallel interface, 0: enable serial interface. le_synco# - led output data stream envelop system clock, power, and ground pins a16 s_clk input system clock at 133 mhz u26 s_rst# input ? st reset input u30 resout# output reset phy b1 dev_cfg[0] input w/ pull down not used b28 dev_cfg[1] input w/ pull down not used ae7, ae9, f10, f21, f22, f9, g25, g6, j25, j6, k25, k6, aa25, aa6, ab25, ab6, ad25, ae10, ae21, ae22 vdd power core +2.5 volt dc supply v14, v15, v16, v17, v18, f16, f24, f25, f6, f7, n13, n14, n15, n16, n17, n18, p13, p14, p15, p16, p17, p18, r13, r14, r15, r16, r17, r18, r25, r6, t13, t14, t15, t16, t17, t18, t25, t6, u13, u14, u15, u16, u17, u18, v13, ad6, ae15, ae16, ae24, ae25, ae6, f15 vss ground ground a1, c28 avdd power analog dc supply e5, e25 avss ground analog ground ball no(s) symbol i/o description
data sheet MVTX2803Ag 113 semicmf.019 ae12, ae13, ae14, ae17, ae18, ae19, f12, f13, f14, f17, f18, f19, m25, m6, n25, n6, p25, p6, u25, u6, v25, v6, w25, w6 vdd33 power i/o +3.3 volt dc supply bootstrap pins (default= pull up, 1= pull up 0= pull down) ad2 g0_tx_en default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs ab5 g0_tx_er default: pcs ak2 g1_tx_en default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs aj3 g1_txer default: pcs ah8 g2_tx_en default: pcs giga2 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs ak9 g2_tx_er default: pcs ag13 g3_tx_en default: pcs giga3 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs aj14 g3_tx_er default: pcs ak19 g4_tx_en default: pcs giga4 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs ah20 g4_tx_er default: pcs ball no(s) symbol i/o description
MVTX2803Ag data sheet semicmf.019 114 ah25 g5_tx_en default: pcs giga5 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs af25 g5_tx_er default: pcs ag29 g6_tx_en default: pcs giga6 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs af30 g6_tx_er default: pcs y27 g7_tx_en default: pcs giga7 mode: g0_txen g0_txer 0 0 mii 0 1 2g 1 0 gmii 1 1 pcs ab27` g7_tx_er default: pcs after reset t_d[15:0] are used by the led interface t30 t_d[0] 1 giga link active status 0 ? active low 1 ? active high t29 t_d[1] 1 power saving 0 ? no power saving 1 ? power saving stop mac clock if no mac activity. t28 t_d[2] 1 - must be 0 (use external pull down) u27 t_d[3] 1 hot plug port module detection enable 0 ? module detection enable 1 ? module detection disable t27 t_d[4] 1 ? must be 0 ( use external pull down) r27 t_d[5] 1 sram memory size 0 ? 512k sram 1 ? 256k sram t26 t_d[6] 1 cpu port mode 0 ? 8 bit cpu data bus 1 ? 16 bit cpu data bus ball no(s) symbol i/o description
data sheet MVTX2803Ag 115 semicmf.019 r28 t_d[7] 1 fdb memory depth 1? one memory layer 0 ? two memory layers la_a[20], lb_a[20] 11 fdb memory size 11 - 2m per bank = 4m total 10 - 1m per bank = 2m total 0x - 512k per bank = 1m total r29 t_d[8] 1 eeprom installed 0 ? eeprom is installed 1 ? eeprom is not installed r30 t_d[9] 1 mct aging enable 0 ? mct aging disable 1 ? mct aging enable r26 t_d[10] 1 fcb handle aging enable 0 ? fcb handle aging disable 1 ? fcb handle aging enable p27 t_d[11] 1 timeout reset enable 0 ? timeout reset disable 1 ? timeout reset enable issue reset if any state machine did not go back to idle for 5sec. p28 t_d[12] 1 speedup test 0 ? enable test speed up. do not use. 1 ? disable test speed up p29 t_d[13] 1 enable debounce for strobe signal 0 ? disable debounce on strobe signal using 1msec clock ? do not use. 1 ? enable debounce on strobe signal p30 t_d[14] 1 cpu installed 0 ? cpu installed. 1 ? cpu is not installed. p26 t_d[15] 1 external ram test 0 ? perform the infinite loop of zbt ram bist. debug test only 1 ? regular operation. ball no(s) symbol i/o description
MVTX2803Ag data sheet semicmf.019 116 notes: # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od= output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver n30, n29, n28 p_d[2:0] 11 1 zbt ram la_clk turning 3?b000 - control by reg. lclkcr [2:0] 3?b001 - delay by method # 0 3?b010 - delay by method # 1 3?b011 - delay by method # 2 3?b100 - delay by method # 3 3?b101 - delay by method # 4 3?b110 - delay by method # 5 3?b111 - delay by method # 6 ? use this method m30, m29, m28 p_d[5:3] 111 zbt ram lb_clk turning 3?b000 - control by reg. lclkcr [6:4] 3?b001 - delay by method # 0 3?b010 - delay by method # 1 3?b011 - delay by method # 2 3?b100 - delay by method # 3 3?b101 - delay by method # 4 3?b110 - delay by method # 5 3?b111 - delay by method # 6? use this method l29, l28, n26 p_d[8:6] 111 sbram b_clk turning 3?b000 - control by bclkcr [2:0] 3?b001 - delay by method # 0 3?b010 - delay by method # 1 3?b011 - delay by method # 2 3?b100 - delay by method # 3 3?b101 - delay by method # 4 3?b110 - delay by method # 5 3?b111 - delay by method # 6? use this method ball no(s) symbol i/o description
data sheet MVTX2803Ag 117 semicmf.019 11.4 ball signal name ball no. signal name ball no. signal name ball no. signal name a1 avdd m1 la_d[34] y2 la_a[13] b1 dev_cfg[0] m2 la_d[35] v4 la_a[14] b2 la_d[0] m3 la_d[36] y1 la_a[15] c2 la_clk k4 la_d[37] aa3 la_a[16] c1 la_d[1] n1 la_d[38] aa2 la_a[17] d1 la_d[2] p5 la_d[39] v5 la_a[18] c3 la_d[3] n2 la_d[40] aa1 la_a[19] e4 la_d[4] l5 la_d[41] w4 la_a[20] d2 la_d[5] n3 la_d[42] y4 g0_crs/link e3 la_d[6] p1 la_d[43] aa4 gref_clk[0] e2 la_d[7] p2 la_d[44] ab4 g0_txclk e1 la_d[8] p3 la_d[45] ab3 g0_txd[0] d3 la_d[9] l4 la_d[46] w5 g0_txd[1] f1 la_d[10] r5 la_d[47] ab2 g0_txd[2] f2 la_d[11] m5 la_d[48] ab1 mii_tx_clk[0] f3 la_d[12] r1 la_d[49] ac3 g0_txd[3] f4 la_d[13] r2 la_d[50] y5 g0_txd[4] f5 la_d[14] r3 la_d[51] ac2 g0_txd[5] g1 la_d[15] r4 la_d[52] ac1 g0_rxclk g2 la_d[16] m4 la_d[53] ad3 g0_col g5 la_d[17] t4 la_d[54] ad4 g0_txd[6] g4 la_d[18] t3 la_d[55] aa5 g0_txd[7] g3 la_d[19] n5 la_d[56] ad2 g0_tx_en h1 la_d[20] t2 la_d[57] ab5 g0_tx_er h2 la_d[21] t1 la_d[58] ad1 g0_rxd[0] h3 la_d[22] u4 la_d[59] ae4 g0_rxd[1] j1 la_d[23] u3 la_d[60] ac4 g0_rxd[2] h5 la_d[24] n4 la_d[61] ae3 g0_rxd[3] j2 la_d[25] u2 la_d[62] ae2 g0_rxd[4] j3 la_d[26] u1 la_d[63] ae1 g0_rxd[5]
MVTX2803Ag data sheet semicmf.019 118 j4 la_d[27] v3 la_a[3] ac5 g0_rxd[6] k1 la_d[28] p4 la_a[4] af1 g0_rxd[7] h4 la_d[29] v2 la_a[5] ad5 g0_rx_dv k2 la_d[30] v1 la_a[6] af2 g0_rx_er j5 la_d[31] t5 la_a[7] af3 gref_clk[1] k3 la_cs0# w3 la_a[8] ag2 g1_txclk l1 la_cs1# w2 la_a[9] ag3 g1_crs/link l2 la_rw# w1 la_a[10] ae5 g1_txd[0] l3 la_d[32] u5 la_a[11] ag1 g1_txd[1] k5 la_d[33] y3 la_a[12] ah1 g1_txd[2] ah2 g1_txd[3] ag10 g2_rxclk ag19 g4_txd[1] aj2 g1_txd[4] ak10 g2_col ak17 g4_txd[2] aj1 g1_txd[5] aj10 g2_rxd[6] af20 g4_txd[3] ak1 g1_txd[6] ag11 g2_rxd[7] ah18 g4_txd[4] ag4 g1_txd[7] ah10 g2_rx_dv aj18 g4_txd[5] ak2 g1_tx_en ag12 g2_rx_er ak18 mii_tx_clk[4] ah3 mii_tx_clk[1] ak11 g3_crs/link ah19 g4_txd[6] aj3 g1_tx_er aj11 gref_clk[3] aj19 g4_txd[7] ah4 g1_rxd[0] ah11 g3_txclk ak19 g4_tx_en ak3 g1_rxd[1] ak12 g3_txd[0] ah20 g4_tx_er af4 g1_rxd[2] af12 g3_txd[1] aj20 g4_rxd[0] ak4 g1_rxd[3] aj12 g3_txd[2] af21 g4_rxd[1] ah5 g1_rxclk ah12 g3_txd[3] ak20 g4_rxd[2] aj4 g1_col ak13 g3_txd[4] ah21 g4_rxclk ag6 g1_rxd[4] aj13 mii_tx_clk[3] aj21 g4_col af5 g1_rxd[5] ah13 g3_txd[5] ak21 g4_rxd[3] aj5 g1_rxd[6] af13 g3_txd[6] af22 g4_rxd[4] af6 g1_rxd[7] ak14 g3_txd[7] ag20 g4_rxd[5] ak5 g1_rx_dv ag13 g3_tx_en ag21 g4_rxd[6] ak6 g1_rx_er aj14 g3_t x_er ag22 g4_rxd[7] aj6 gref_clk[2] ah14 g3 _rxclk ah22 g4_rx_dv ag5 g2_txclk af14 g3_col aj22 gref_clk[5] ah6 g2_crs/link ag14 g3_rxd[0] ak22 g5_txclk ball no. signal name ball no. signal name ball no. signal name
data sheet MVTX2803Ag 119 semicmf.019 af7 g2_txd[0] ak15 cm_clk ah23 g4_rx_er ak7 g2_txd[1] af17 ind _cm ag23 g5_crs/link aj7 g2_txd[2] aj15 g3_rxd[1] aj23 g5_txd[0] ag8 g2_txd[3] ah15 g3_r xd[2] ak23 g5_txd[1] ag7 g2_txd[4] af15 g3_rxd[3] af23 g5_txd[2] ah7 mii_tx_clk[2] af18 g3_rxd[4] ah24 g5_txd[3] ak8 g2_txd[5] ag15 g3_rxd[5] af24 g5_txd[4] aj8 g2_txd[6] af16 g3_rxd[6] ag24 g5_txd[5] af8 g2_txd[7] ag16 g3_rxd[7] aj24 g5_txd[6] ah8 g2_tx_en ah16 g3_rx_dv ak24 g5_txd[7] ak9 g2_tx_er af19 g3_rx_er ag25 mii_tx_clk[5] aj9 g2_rxd[0] aj16 m_mdc ah25 g5_tx_en ah9 g2_rxd[1] ag18 m_mdio af25 g5_tx_er af9 g2_rxd[2] ak16 g4_crs/link aj25 g5_rxd[0] ag9 g2_rxd[3] ag17 gref_clk[4] ag26 g5_rxd[1] af10 g2_rxd[4] ah17 g4_txclk ak25 g5_rxd[2] af11 g2_rxd[5] aj17 g4_txd[0] ak26 g5_rxclk aj26 g5_col aa27 g7_t xd[3] p29 t_d[13] ah26 g5_rxd[3] ab30 g 7_txd[4] p30 t_d[14] aj27 g5_rxd[4] ab29 g 7_txd[5] p26 t_d[15] af26 g5_rxd[5] y26 g7_txd[6] n28 p_d[0] ah27 g5_rxd[6] ab28 g 7_txd[7] n29 p_d[1] ak27 g5_rxd[7] y27 g7_tx_en n30 p_d[2] ak28 g5_rx_dv ab27 g7_tx_er m28 p_d[3] aj28 g5_rx_er aa30 mii_tx_clk[7] m29 p_d[4] aj29 g6_crs/link aa2 9 g7_rxclk m30 p_d[5] ak29 mii_tx_clk[6] aa28 g7_col n26 p_d[6] ak30 gref_clk[6] y30 g7_rxd[0] l28 p_d[7] aj30 g6_txd[0] w27 g7_rxd[1] l29 p_d[8] ah28 g6_txd[1] y29 g 7_rxd[2] n27 p_d[9] ah29 g6_txd[2] w26 g 7_rxd[3] l30 p_d[10] ag27 g6_txd[3] y28 g7_rxd[4] k28 p_d[11] ag28 g6_txd[4] w30 g7_rxd[5] k29 p_d[12] ball no. signal name ball no. signal name ball no. signal name
MVTX2803Ag data sheet semicmf.019 120 ah30 g6_txclk w29 g7_rxd[6] k30 p_d[13] ag30 g6_txd[5] v26 g7_rxd[7] l27 p_d[14] af28 g6_txd[6] w28 g7_rx_dv k27 p_d[15] ae26 g6_txd[7] v27 g7_rx_er m26 p_a[0] ag29 g6_tx_en v30 le_do j27 p_a[1] af27 g6_rxclk v29 le_clk0 j28 p_a[2] af29 g6_col v28 le_synco# j29 p_we# af30 g6_tx_er u26 s_rst# j30 p_rd# ad26 g6_rxd[0] u30 resout# l26 p_cs# ae30 g6_rxd[1] u29 t_mode[0] h28 p_int# ac26 g6_rxd[2] u28 t_mode[1] m27 b_d[0] ae29 g6_rxd[3] t30 t_d[0] h29 b_d[1] ac27 g6_rxd[4] t29 t_d[1] h30 b_d[2] ae28 g6_rxd[5] t28 t_d[2] g28 b_d[3] ae27 g6_rxd[6] u27 t_d[3] g27 b_d[4] ab26 g6_rxd[7] t27 t_d[4] k26 b_d[5] ad30 g6_rx_dv r27 t_d[5] g29 b_d[6] ad29 gref_clk[7] t26 t_d[6] g30 b_d[7] ad27 g6_rx_er r28 t_d[7] h27 b_d[8] ad28 g7_txclk r29 t_d[8] f27 b_d[9] ac30 g7_crs/link r30 t_d[9] f28 b_d[10] aa26 g7_txd[0] r26 t_d[10] f29 b_d[11] ac29 g7_txd[1] p27 t_d[11] f30 b_d[12] ac28 g7_txd[2] p28 t_d[12] j26 b_d[13] e30 b_d[14] a23 b_a[12] e14 lb_d[49] h26 b_d[15] b23 b_a[13] c15 lb_d[48] e29 b_d[16] c23 b_a[14] b15 lb_d[47] e26 b_d[17] e22 b_a[15] e13 lb_d[46] d29 b_d[18] a22 b_a[16] a15 lb_d[45] e28 b_d[19] b22 b_a[17] d14 lb_d[44] g26 b_d[20] c22 b_a[18] c14 lb_d[43] d30 b_d[21] e21 lb_a[20] d13 lb_d[42] c30 b_d[22] d22 lb_a[19] b14 lb_d[41] ball no. signal name ball no. signal name ball no. signal name
data sheet MVTX2803Ag 121 semicmf.019 e27 b_d[23] d20 lb_a[18] a14 lb_d[40] c29 b_clk e20 lb_a[17] c13 lb_d[39] d28 b_d[24] d21 lb_a[16] e12 lb_d[38] b30 b_d[25] a21 lb_a[15] b13 lb_d[37] f26 nc1 d19 lb_a[14] a13 lb_d[36] d26 nc2 b21 lb_a[13] d12 lb_d[35] a30 nc3 c21 lb_a[12] c12 lb_d[34] a29 nc4 a20 lb_a[11] b12 lb_d[33] b29 nc5 b20 lb_a[10] a12 lb_d[32] e25 agnd e19 lb_a[9] c11 lb_rw# b28 dev_cfg[1] c20 lb_a[8] e11 lb_cs1# c28 avdd a19 lb_a[7] b11 lb_cs0# a28 b_d[26] b19 lb_ a[6] a11 lb_d[31] a27 b_d[27] e18 lb_ a[5] e10 lb_d[30] c27 b_d[28] c19 lb_a[4] c10 lb_d[29] d27 b_d[29] a18 lb_a[3] b10 lb_d[28] b27 b_d[30] d18 lb_d[63] e9 lb_d[27] e24 b_d[31] b18 lb_d[62] a10 lb_d[26] d25 b_adsc# c18 lb_d[61] d11 lb_d[25] b26 b_we# a17 lb_d[60] d10 lb_d[24] a26 b_oe# e17 lb_d[59] d8 lb_d[23] a25 b_a[2] b17 lb_d[58] d9 lb_d[22] b25 b_a[3] c17 lb_d[57] c9 lb_d[21] c26 b_a[4] e16 lb_d[56] b9 lb_d[20] c25 b_a[5] d17 lb_d[55] a9 lb_d[19] e23 b_a[6] a16 s_clk c8 lb_d[18] a24 b_a[7] b16 lb_d[54] b8 lb_d[17] b24 b_a[8] e15 lb_d[53] a8 lb_d[16] d23 b_a[9] c16 lb_d[52] c7 lb_d[15] d24 b_a[10] d16 lb_d[51] e7 lb_d[14] c24 b_a[11] d15 lb_d[50] d7 lb_d[13] b7 lb_d[12] p15 vss ae7 vdd e8 lb_d[11] p16 vss ae9 vdd ball no. signal name ball no. signal name ball no. signal name
MVTX2803Ag data sheet semicmf.019 122 a7 lb_d[10] p17 vss f10 vdd d6 lb_d[9] p18 vss f21 vdd c6 lb_d[8] r13 vss f22 vdd e6 lb_d[7] r14 vss f9 vdd b6 lb_d[6] r15 vss g25 vdd a6 lb_d[5] r16 vss g6 vdd a5 lb_d[4] r17 vss j25 vdd b5 lb_d[3] r18 vss j6 vdd c5 lb_d[2] r25 vss k25 vdd b4 lb_d[1] r6 vss k6 vdd d5 lb_clk t13 vss ae12 vd33 a4 lb_d[0] t14 vss ae13 vd33 a3 scan_en t15 vss ae14 vd33 e5 agnd t16 vss ae17 vd33 c4 nc6 t17 vss ae18 vd33 b3 nc7 t18 vss ae19 vd33 d4 nc8 t25 vss f12 vd33 a2 nc9 t6 vss f13 vd33 ad6 vss u13 vss f14 vd33 ae15 vss u14 vss f17 vd33 ae16 vss u15 vss f18 vd33 ae24 vss u16 vss f19 vd33 ae25 vss u17 vss m25 vd33 ae6 vss u18 vss m6 vd33 f15 vss v13 vss n25 vd33 f16 vss v14 vss n6 vd33 f24 vss v15 vss p25 vd33 f25 vss v16 vss p6 vd33 f6 vss v17 vss u25 vd33 f7 vss v18 vss u6 vd33 n13 vss aa25 vdd v25 vd33 n14 vss aa6 vdd v6 vd33 n15 vss ab25 vdd w25 vd33 ball no. signal name ball no. signal name ball no. signal name
data sheet MVTX2803Ag 123 semicmf.019 11.5 ac/dc timing 11.5.1 absolute maximum ratings storage temperature -65c to +150c operating temperature -40c to +85c supply voltage vdd33 with respect to vss +3.0 v to +3.6 v supply voltage vdd with respect to vss +2.38 v to +2.75 v voltage on input pins -0.5 v to (vdd33 + 3.3 v) caution: stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods ma y affect device reliability. functionality at or above these limits is not implied. 11.5.2 dc electrical characteristics vdd33 = 3.0 v to 3.6 v (3.3v +/- 10%)t ambient = -40c to +85c vdd = 2.5v +10% - 5% 11.5.3 recommended operation conditions n16 vss ab6 vdd w6 vd33 n17 vss ad25 vdd n18 vss ae10 vdd p13 vss ae21 vdd p14 vss ae22 vdd symbol parameter description preliminary unit min type max f osc frequency of operation 133 mhz i dd1 supply current ? @ 133 mhz (3.3v supply) 720 930 ma i dd2 supply current ? @ 133 mhz (2.5v supply)) 1400 1700 ma v oh output high voltage (cmos) vdd33 - 0.5 v v ol output low voltage (cmos) 0.5 v v ih-ttl input high voltage (ttl 5v tolerant) vdd33 x 70% vdd33 + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) vcc x 30% v i ih-5vt input leakage current (0.1 v < v in < vdd33) 10 a i il-5vt output leakage current (0.1 v < v out < vdd33) a c in input capacitance 5 pf ball no. signal name ball no. signal name ball no. signal name
MVTX2803Ag data sheet semicmf.019 124 11.6 local frame buffer zbt sram memory interface 11.6.1 local zbt sram memory interface a: figure 6 - local memory interface ? input setup and hold timing figure 7 - local memory interface - output valid delay timing c out output capacitance 5 pf c i/o i/o capacitance 7 pf symbol parameter description preliminary unit min type max la_clk la_d[63:0] l1 l2 l3-max l3-min lb_d[63:0] lb_clk l4-max l4-min lb_a[20:3] l6-max l6-min lb_cs[1,0]#] l3-max l3-min lb_rw#
data sheet MVTX2803Ag 125 semicmf.019 table 6- ac characteristics ? local frame buffer zbt-sram memory interface a 11.6.2 local zbt sram memory interface b: figure 8 - local memory interface ? input setup and hold timing figure 9 - local memory interface - output valid delay timing ac characteristics ? local frame buf fer zbt-sram memory interface a (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 la_d[63:0] input set-up time 2.5 l2 la_d[63:0] input hold time 1 l3 la_d[63:0] output valid delay 3 5 c l = 25pf l4 la_a[20:3] output valid delay 3 5 c l = 30pf l6 la_cs[1:0]# output valid delay 3 5 c l = 30pf l9 la_we# output valid delay 3 5 c l = 25pf lb_clk lb_d[63:0] l1 l2 l3-max l3-min lb_d[63:0] lb_clk l4-max l4-min lb_a[20:3] l6-max l6-min lb_cs[1,0]#] l9-max l9-min lb_rw#
MVTX2803Ag data sheet semicmf.019 126 table 7- local frame buffer zbt-sram memory interface b 11.7 local switch database sbram memory interface 11.7.1 local sbram memory interface: figure 10 - local memory interfa ce ? input setup and hold timing figure 11 - local memory inte rface - output valid delay timing local frame buffer zbt-sr am memory interface b (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 lb_d[63:0] input set-up time 2.5 l2 lb_d[63:0] input hold time 1 l3 lb_d[63:0] output valid delay 3 5 c l = 25pf l4 lb_a[20:3] output valid delay 3 5 c l = 30pf l6 lb_cs[1:0]# output valid delay 3 5 c l = 30pf l9 lb_we# output valid delay 3 5 c l = 25pf b_clk b_d[31:0] l1 l2 l3-max l3-min b_d[31:0] b_clk l4-max l4-min b_a[18:2] l6-max l6-min b_adsc# l10-max l10-min b_we# l11-max l11-min b_oe#
data sheet MVTX2803Ag 127 semicmf.019 table 8- ac characteristics ? local switch database sbram memory interface 11.8 ac characteristics 11.8.1 media independent interface figure 12 - ac characteristics ? media independent interface figure 13 - ac characteristics ? media independent interface ac characteristics ? local switch database sbram memory interface (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 b_d[63:0] input set-up time 2.5 l2 b_d[63:0] input hold time 1 l3 b_d[63:0] output valid delay 3 5 c l = 25pf l4 b_a[20:3] output valid delay 3 5 c l = 30pf l6 b_adsc# output valid delay 3 5 c l = 30pf l10 b_we# output valid delay 3 5 c l = 25pf l11 b_oe# output valid delay 3 4 c l = 25pf mii_txclk[7:0] g[7:0]_txen g[7:0]_txd[3:0] m6-max m6-min m7-max m7-min g[7:0]_rxclk g[7:0]_rxd[3:0] g[7:0]_crs_dv m2 m4 m3 m5
MVTX2803Ag data sheet semicmf.019 128 table 9- ac characteristics ? media independent interface 11.8.2 gigabit media independent interface figure 14 - ac characteristics- gmii figure 15 - ac characteristics ? gigabit media independent interface ac characteristics ? medi a independent interface (mii_txclk & g_rxclk = 25mhz) symbol parameter min (ns) max (ns) note: m2 g[7:0]_rxd[3:0] input setup time 4 m3 g[7:0]_rxd[3:0] input hold time 1 m4 g[7:0]_crs_dv input setup time 4 m5 g[7:0]_crs_dv input hold time 1 m6 g[7:0]_txen output delay time 3 11 c l = 20 pf m7 g[7:0]_txd[3:0] output delay time 3 11 c l = 20 pf g12-max g12-min g[7:0]_txd[7:0] g[7:0]_txclk g13 max g13-min g[7:0]_tx_en g14-max g14-min g[7:0]_tx_er g[7:0]_rxclk g[7:0]_rxd[7:0] g[7:0]_rx_dv g3 g5 g[7:0]_rx_er g1 g2 g4 g6 g7 g8 g[7:0]_rx_crs
data sheet MVTX2803Ag 129 semicmf.019 table 10- ac characteristics ? gigabit media independent interface 11.8.3 pcs interface figure 16 - ac characteristics ? pcs interface figure 17 - ac characteristics ? pcs interface ac characteristics ? gigabi t media independent interface (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: g1 g[7:0 ]_rxd[7:0] input setup times 2 g2 g[7:0 ]_rxd[7:0] input hold times 1 g3 g[7:0 ]_rx_dv input setup times 2 g4 g[7:0 ]_rx_dv input hold times 1 g5 g[7:0 ]_rx_er input setup times 2 g6 g[7:0 ]_rx_er input hold times 1 g7 g[7:0 ]_crs input setup times 2 g8 g[7:0 ]_crs input hold times 1 g12 g[7:0 ]_txd[7:0] output delay times 1 5 c l = 20pf g13 g[7:0 ]_tx_en output delay times 1 5 c l = 20pf g14 g[7:0 ]_tx_er output delay times 1 5 c l = 20pf g[7:0]_txclk g[7:0]_txd[9:0] g30-max g30-min g21 g22 g23 g24 g25 g26 g[7:0]_rxclk1 g[7:0]_rxclk g[7:0]_rxd[9:0] g[7:0]_rx+crs
MVTX2803Ag data sheet semicmf.019 130 table 11- ac characteristics ? pcs interface 11.8.4 led interface figure 18 - ac characteristics ? led interface table 12- ac characteristics ? led interface ac characteristics ? pcs interface (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: g21 g[7:0 ]_rxd[9:0] input setup times ref to g_rxclk 2 g22 g[7:0 ]_rxd[9:0] input ho ld times ref to g_rxclk 1 g23 g[7:0 ]_rxd[9:0] input setup times ref to g_rxclk1 2 g24 g[7:0 ]_rxd[9:0] input ho ld times ref to g_rxclk1 1 g25 g[7:0 ]_crs input setup times 2 g26 g[7:0 ]_crs input hold times 1 g30 g[7:0 ]_txd[9:0] output delay times 1 5 c l = 20pf ac characteristics ? led interface variable freq. symbol parameter min(ns) max (ns) note: le5 led_syn output valid delay 1 7 c l = 30pf le6 led_bit output valid delay 1 7 c l = 30pf led_clk] led_syn led_bit le5-max le5-min le6-max le6-min
data sheet MVTX2803Ag 131 semicmf.019 11.8.5 mdio input setup and hold timing figure 19 - mdio input setup and hold timing figure 20 - mdio output delay timing table 13- mdio timing 11.8.6 i 2 c input setup timing figure 21 - i 2 c input setup timing figure 22 - i 2 c output delay timing mdio timing 1mhz symbol parameter min (ns) max (ns) note: d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50pf mdc mdio d1 d2 mdc mdio d3-max d3-min sdl sda s1 s2 scl sda s3-max s3-min
MVTX2803Ag data sheet semicmf.019 132 table 14- i 2 c timing 11.8.7 serial interface setup timing figure 23 - serial interface setup timing figure 24 - serial interface output delay timing table 15- serial interface timing i 2 c timing 500khz symbol parameter min (ns) max (ns) note: s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 1 20 c l = 30pf * open drain output. low to high transistor is controlled by external pullup resistor. serial interface timing (sclk =133 mhz) symbol parameter min (ns) max (ns) note: d1 ps_di setup time 20 d2 ps_di hold time 10 d3 ps_do output delay time 1 50 c l = 100pf d4 strobe low time 5 s d5 strobe high time 5 s d4 d5 d2 d1 d2 d1 strobe ps_di ps_d0 d3-max d3-min strobe
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